lanlingshan

 

2012年3月16日

ModelSim-Altera Precompiled Libraries

摘要: Note: Do not compile any Altera model files that are located in the quartus/eda/sim_lib directory. Note: VHDL logical libraries have the names listed in the table. VHDL logical libraries have a _ver suffix. Logical Library NameLibrary DescriptionarriagxArriaGXarriagx_hssiArriaGX devices with tra... 阅读全文

posted @ 2012-03-16 10:46 lanlingshan 阅读(331) 评论(0) 推荐(0) 编辑

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