testbench中initial部分clk没有赋初值导致clk输出X
摘要：
/*`timescale 1ns/100ps`define clk_cycle 50module testbench1; reg clk,reset,nbusy; reg [7:0]data; wire ce,sck,si; always #`clk_cycle clk=~clk; initial begin reset=1; #100 reset=0; #100 reset=1; #100000 $stop; endendmodule */`timescale 1ns/100ps`define clk_cycle 50module testbench2; reg clk,reset; wi. 阅读全文
posted @ 2012-02-16 17:28 lanlingshan 阅读(581) 评论(0) 推荐(0) 编辑
