2020年5月19日
Verilog HDL刷题笔记（02）
摘要： 16.Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, 阅读全文
posted @ 2020-05-19 21:34 Kraken 阅读(7587) 评论(0) 推荐(0) 编辑