Verilog HDL刷题笔记（06）(Circuit-Combinational Logic-Arithmetic Circuit)

66.Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.

module top_module( 
    input a, b,
    output cout, sum );
    assign sum = a^b;
    assign cout = a&b;
endmodule

67.Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out.

module top_module( 
    input a, b, cin,
    output cout, sum );
    assign cout = a&b|a&cin|b&cin;
    assign sum = a^b^cin;
endmodule

68.Now that you know how to build a full adder, make 3 instances of it to create a 3-bit binary ripple-carry adder. The adder adds two 3-bit numbers and a carry-in to produce a 3-bit sum and carry out. To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder. cout[2] is the final carry-out from the last full adder, and is the carry-out you usually see.

module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
    fadd fadd1 (a[0],b[0],cin,cout[0],sum[0]);
    fadd fadd2 (a[1],b[1],cout[0],cout[1],sum[1]);
    fadd fadd3 (a[2],b[2],cout[1],cout[2],sum[2]);
endmodule

module fadd( 
    input a, b, cin,
    output cout, sum );
    assign cout = a&b|a&cin|b&cin;
    assign sum = a^b^cin;
endmodule

69.Implement the following circuit:

module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);
    wire [2:0] cout;
    wire cin;
    assign cin = 1'b0;
    fadd fadd0 (x[0],y[0],cin,cout[0],sum[0]);
    fadd fadd1 (x[1],y[1],cout[0],cout[1],sum[1]);
    fadd fadd2 (x[2],y[2],cout[1],cout[2],sum[2]);
    fadd fadd3 (x[3],y[3],cout[2],sum[4],sum[3]);
endmodule

module fadd( 
    input a, b, cin,
    output cout, sum );
    assign cout = a&b|a&cin|b&cin;
    assign sum = a^b^cin;
endmodule
//
//答案这操作很6
//
module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);

    // This circuit is a 4-bit ripple-carry adder with carry-out.
    assign sum = x+y;    // Verilog addition automatically produces the carry-out bit.

    // Verilog quirk: Even though the value of (x+y) includes the carry-out, (x+y) is still considered to be a 4-bit number (The max width of the two operands).
    // This is correct:
    // assign sum = (x+y);
    // But this is incorrect:
    // assign sum = {x+y};    // Concatenation operator: This discards the carry-out
endmodule

70.Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.

HINT:A signed overflow occurs when adding two positive numbers produces a negative result, or adding two negative numbers produces a positive result. There are several methods to detect overflow: It could be computed by comparing the signs of the input and output numbers, or derived from the carry-out of bit n and n-1.

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);
    wire c;
    assign {c,s} = a+b;
    assign overflow = ~a[7]&~b[7]&s[7]|a[7]&b[7]&~s[7];
endmodule

71.Create a 100-bit binary adder. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out.

71.Create a 100-bit binary adder. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out.

module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
    assign {cout,sum} = a+b+cin;
endmodule

72.You are provided with a BCD (binary-coded decimal) one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.

module bcd_fadd {
    input [3:0] a,
    input [3:0] b,
    input     cin,
    output   cout,
    output [3:0] sum );

Instantiate 4 copies of bcd_fadd to create a 4-digit BCD ripple-carry adder. Your adder should add two 4-digit BCD numbers (packed into 16-bit vectors) and a carry-in to produce a 4-digit sum and carry out.

module top_module( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
    wire [3:0] ccout;
    bcd_fadd add0 (a[3:0],b[3:0],cin,ccout[0],sum[3:0]);
    bcd_fadd add1 (a[7:4],b[7:4],ccout[0],ccout[1],sum[7:4]);
    bcd_fadd add2 (a[11:8],b[11:8],ccout[1],ccout[2],sum[11:8]);
    bcd_fadd add3 (a[15:12],b[15:12],ccout[2],ccout[3],sum[15:12]);
    assign cout = ccout[3];
endmodule
//Warning (10230): Verilog HDL assignment warning at tb_modules.sv(8): truncated value with size 32 to match size of target (4) 
14 //File: /var/www/verilog/work/vlgRbJv4p_dir/tb_modules.sv Line: 8