System Verilog (5) 联合数组

联合数组，associative arrays， 为了充分利用内存的零散空间🔍

语法格式： data_type associative_array_name [index data type] ;

查看代码

module assoc_array;
  int assoc1 [string] ;
  int assoc2 [int] ;
  string assoc3 [string];
  initial begin
    assoc1= '{"orange": 100, "banana": 60};
    assoc2= '{1:40, 2:40};
    assoc3= '{"element1": "orange", "element2": "banana"};
    $display("assoc1 is %p", assoc1);
    $display("assoc2 is %p", assoc2);
    $display("assoc3 is %p", assoc3);
  end
endmodule

编译结果

# Loading sv_std.std
# Loading work.assoc_array(fast)
# 
# vsim -voptargs=+acc=npr
# run -all
# assoc1 is '{"banana":60, "orange":100 }
# assoc2 is '{1:40, 2:40 }
# assoc3 is '{"element1":"orange", "element2":"banana" }
# exit
# End time: 02:13:25 on Mar 31,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
Done