The complete timer

合集 - Verilog学习(62)

1.Decade counter2024-04-102.Four-bit binary counter2024-04-103.Decade counter again2024-04-104.Slow decade counter2024-04-105.Counter 1-122024-04-106.Counter 10002024-04-107.4-digit decimal counter2024-04-108.12-hour clock2024-04-109.Hdlbits博文分布2024-04-1010.4-bit shift register2024-04-1111.Left/right rotator2024-04-1112.Left/right arithmetic shift by 1 or 82024-04-1113.5-bit LFSR2024-04-1114.3-bit LFSR2024-04-1115.32-bit LFSR2024-04-1116.Shift register2024-04-1117.Shift register(2)2024-04-1118.3-input LUT2024-04-1119.Rule 902024-04-1220.Rule 1102024-04-1221.Conway's Game of Life 16x162024-04-1222.Simple FSM1(asynchronous reset)2024-04-1423.Simple FSM1(synchronous reset)2024-04-1424.Simple FSM2(asynchronous reset)2024-04-1425.Simple FSM2(synchronous reset)2024-04-1426.Simple state transition 32024-04-1427.Simple one-hot state transition 32024-04-1428.Simple FSM 3（asynchronous reset）2024-04-1429.Simple FSM 3（synchronous reset）2024-04-1430.Design a Moore FSM2024-04-1431.Lemmings 12024-04-1432.Lemmings 22024-04-1433.Lemmings 32024-04-1534.Lemmings 42024-04-1535.One-hot FSM2024-04-1536.PS/2 packet parser2024-04-1537.PS/2 packet parser and datapath2024-04-1538.Serial receiver2024-04-1539.Serial receiver and datapath2024-04-1540.Serial receiver with parity checking2024-04-1541.Sequence recognition2024-04-1642.Q8:Design a Mealy FSM2024-04-1643.Q5a:Serial two's complementer(Moore FSM)2024-04-1644.Q5b:Serial two's complementer(Moore FSM)2024-04-1645.Q3a:FSM2024-04-1646.Q3b:FSM2024-04-1647.Q3c:FSM logic2024-04-1648.Q6b:FSM next-state logic2024-04-1649.Q6c:FSM next-state logic2024-04-1650.Q6:FSM2024-04-1651.Q2a：FSM2024-04-1652.Q2:One-hot FSM equations2024-04-1653.Q2a: FSM2024-04-1654.Q2b：Another FSM2024-04-1655.Counter with period 10002024-04-1656.4-bit shift register and down counter2024-04-1657.FSM:Sequence 1101 recognizer2024-04-1658.FSM:Enable shift register2024-04-1659.FSM:The complete FSM2024-04-16

60.The complete timer2024-04-16

61.FSM:One-hot logic equations2024-04-1662.UART2024-04-16

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module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    reg [9:0] counter;
    reg clkn;
    reg [4:0] delay; // 防 count=4'b1111(4'hf)时，delay=count+4'd1=0溢出。
    reg [3:0] state,next_state;
    parameter [3:0] S = 4'd0,S1 = 4'd1,S11 = 4'd2,S110 = 4'd3,B0 = 4'd4,B1 = 4'd5,B2 = 4'd6,B3 = 4'd7,Count2 = 4'd8,Wait = 4'd9;
    // state transfer
    always@(*) begin
        case(state)
            S: begin
                next_state = (data)? S1:S;
            end
            S1: begin
                next_state = (data)? S11:S;
            end
            S11: begin
                next_state = (data)? S11:S110;
            end
            S110: begin
                next_state = (data)? B0:S;
            end
            B0: begin
                next_state = B1;
            end
            B1: begin
                next_state = B2;
            end
            B2: begin
                next_state = B3;
            end
            B3: begin
                next_state = Count2;
            end
            Count2: begin
                next_state =(delay == 5'd0)? Wait:Count2; 
            end
            Wait: begin
                next_state =(ack)? S:Wait; 
            end
            default: next_state = S;
        endcase
    end
    // flip-flop
    always@(posedge clk) begin
        if(reset)
            state <= S;
        else 
            state <= next_state;
    end
    // output
    always@(posedge clk) begin
        counting <= (next_state == Count2 && !reset)? 1'b1:1'b0; // 这里记得加条件!reset，否则倒数中途reset需要再多隔1cycle，(先变state再变counting)
        done <= (next_state == Wait)? 1'b1:1'b0;
    end
    
    // shift reg
    always@(posedge clk) begin              
        if(state == B0 || state == B1 || state == B2) begin
            count <= {count[2:0],data};
            delay <= {delay[3:0],data};   
            counter <= 10'd0;
        end  
        else if(state == B3) begin
            count <= {count[2:0],data};
            delay <= {delay[3:0],data} + 4'd1;  
            counter <= 10'd0;
        end
        else if(next_state == Count2) begin           
            count <= (count != 4'd0 && counter == 10'd999)? count - 4'd1:count; // 后者亦满足当count=0则其一直保持0,只是输出的形式，真的倒数看delay
            if(delay != 4'd1 && counter == 10'd999) begin //非1的时候，在每一个0进行减
                delay <= delay - 5'd1;
            end
            else if(delay == 5'd1 && counter == 10'd998) begin
                delay <= 5'd0;
            end
            else begin
                delay <= delay;
            end
            counter <= (counter == 10'd999)? 10'd0:counter+10'd1; // frequency divider
        end
        else begin
            counter <= 10'd0;
            count <= 4'd0; // 其他state，count保持0
            delay <= 5'd0;
        end
    end
    
    
endmodule

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