FSM:Enable shift register

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);

    parameter IDLE = 2'd0, ENA = 2'd1, STOP = 2'd2;
    reg [1:0] current_state, next_state;
    reg [2:0] counter;

    always @(*) begin
        case(current_state)
            IDLE:       next_state = ENA;
            ENA:        next_state = (counter == 3'd3) ? STOP : ENA;
            STOP:       next_state = STOP;
            default:    next_state = IDLE;
        endcase
    end

    always @(posedge clk) begin
        if(reset) begin
            current_state <= IDLE;
        end
        else begin
            current_state <= next_state;
        end
    end

    always @(posedge clk) begin
        if(reset) begin
            counter <= 3'd0;
        end
        else begin
            case(next_state)
                IDLE:       counter <= 3'd0;
                ENA:        counter <= counter + 1'b1;
                STOP:       counter <= 3'd0;
                default:    counter <= 3'd0;
            endcase
        end      
    end

    assign shift_ena = current_state == ENA | current_state == IDLE;

endmodule