Q3b:FSM
1.Decade counter2.Four-bit binary counter3.Decade counter again4.Slow decade counter5.Counter 1-126.Counter 10007.4-digit decimal counter8.12-hour clock9.Hdlbits博文分布10.4-bit shift register11.Left/right rotator12.Left/right arithmetic shift by 1 or 813.5-bit LFSR14.3-bit LFSR15.32-bit LFSR16.Shift register17.Shift register(2)18.3-input LUT19.Rule 9020.Rule 11021.Conway's Game of Life 16x1622.Simple FSM1(asynchronous reset)23.Simple FSM1(synchronous reset)24.Simple FSM2(asynchronous reset)25.Simple FSM2(synchronous reset)26.Simple state transition 327.Simple one-hot state transition 328.Simple FSM 3（asynchronous reset）29.Simple FSM 3（synchronous reset）30.Design a Moore FSM31.Lemmings 132.Lemmings 233.Lemmings 334.Lemmings 435.One-hot FSM36.PS/2 packet parser37.PS/2 packet parser and datapath38.Serial receiver39.Serial receiver and datapath40.Serial receiver with parity checking41.Sequence recognition42.Q8:Design a Mealy FSM43.Q5a:Serial two's complementer(Moore FSM)44.Q5b:Serial two's complementer(Moore FSM)45.Q3a:FSM
46.Q3b:FSM
47.Q3c:FSM logic48.Q6b:FSM next-state logic49.Q6c:FSM next-state logic50.Q6:FSM51.Q2a：FSM52.Q2:One-hot FSM equations53.Q2a: FSM54.Q2b：Another FSM55.Counter with period 100056.4-bit shift register and down counter57.FSM:Sequence 1101 recognizer58.FSM:Enable shift register59.FSM:The complete FSM60.The complete timer61.FSM:One-hot logic equations62.UART
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010;
parameter S3 = 3'b011, S4 = 3'b100;
reg [2:0] current_state, next_state;
always @(*) begin
case(current_state)
S0: next_state = x ? S1 : S0;
S1: next_state = x ? S4 : S1;
S2: next_state = x ? S1 : S2;
S3: next_state = x ? S2 : S1;
S4: next_state = x ? S4 : S3;
default:next_state = S0;
endcase
end
always @(posedge clk) begin
if(reset)begin
current_state <= S0;
end
else begin
current_state <= next_state;
end
end
always @(posedge clk) begin
if(reset)begin
z <= 1'b0;
end
else begin
case(next_state)
S3: z <= 1'b1;
S4: z <= 1'b1;
default:z <= 1'b0;
endcase
end
end
endmodule
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