Q3a:FSM

合集 - Verilog学习(62)

1.Decade counter2024-04-102.Four-bit binary counter2024-04-103.Decade counter again2024-04-104.Slow decade counter2024-04-105.Counter 1-122024-04-106.Counter 10002024-04-107.4-digit decimal counter2024-04-108.12-hour clock2024-04-109.Hdlbits博文分布2024-04-1010.4-bit shift register2024-04-1111.Left/right rotator2024-04-1112.Left/right arithmetic shift by 1 or 82024-04-1113.5-bit LFSR2024-04-1114.3-bit LFSR2024-04-1115.32-bit LFSR2024-04-1116.Shift register2024-04-1117.Shift register(2)2024-04-1118.3-input LUT2024-04-1119.Rule 902024-04-1220.Rule 1102024-04-1221.Conway's Game of Life 16x162024-04-1222.Simple FSM1(asynchronous reset)2024-04-1423.Simple FSM1(synchronous reset)2024-04-1424.Simple FSM2(asynchronous reset)2024-04-1425.Simple FSM2(synchronous reset)2024-04-1426.Simple state transition 32024-04-1427.Simple one-hot state transition 32024-04-1428.Simple FSM 3（asynchronous reset）2024-04-1429.Simple FSM 3（synchronous reset）2024-04-1430.Design a Moore FSM2024-04-1431.Lemmings 12024-04-1432.Lemmings 22024-04-1433.Lemmings 32024-04-1534.Lemmings 42024-04-1535.One-hot FSM2024-04-1536.PS/2 packet parser2024-04-1537.PS/2 packet parser and datapath2024-04-1538.Serial receiver2024-04-1539.Serial receiver and datapath2024-04-1540.Serial receiver with parity checking2024-04-1541.Sequence recognition2024-04-1642.Q8:Design a Mealy FSM2024-04-1643.Q5a:Serial two's complementer(Moore FSM)2024-04-1644.Q5b:Serial two's complementer(Moore FSM)2024-04-16

45.Q3a:FSM2024-04-16

46.Q3b:FSM2024-04-1647.Q3c:FSM logic2024-04-1648.Q6b:FSM next-state logic2024-04-1649.Q6c:FSM next-state logic2024-04-1650.Q6:FSM2024-04-1651.Q2a：FSM2024-04-1652.Q2:One-hot FSM equations2024-04-1653.Q2a: FSM2024-04-1654.Q2b：Another FSM2024-04-1655.Counter with period 10002024-04-1656.4-bit shift register and down counter2024-04-1657.FSM:Sequence 1101 recognizer2024-04-1658.FSM:Enable shift register2024-04-1659.FSM:The complete FSM2024-04-1660.The complete timer2024-04-1661.FSM:One-hot logic equations2024-04-1662.UART2024-04-16

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Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. The timing diagram below illustrates the required values of z for different values of w.

Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input.

考虑一个具有输入 s 和 w 的有限状态机。假设 FSM 以名为 A 的复位状态开始， 如下图所示。只要 s = 0，FSM 就会保持在状态 A，当 s = 1 时，它会移动到状态 B。一旦进入状态 B，FSM 就会在接下来的三个状态中检查输入 w 的值 时钟周期。如果 w = 1 恰好是其中两个时钟周期，则 FSM 必须在下一个时钟周期中将输出 z 设置为 1。否则，z 必须为 0。FSM 继续检查 w 接下来的三个时钟周期，依此类推。下面的时序图说明了所需的值 的 z 表示不同的 w 值。

使用尽可能少的状态。请注意，s 输入仅在状态 A 中使用，因此您只需要考虑 w 输入。
题目网站

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
    parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;
    
    reg [1:0] state,next,count;
    
    always@(*)
        begin
            case(state)
                A:next = s ? B : A;
                B:next = C;
                C:next = D;
                D:next = B;
            endcase
        end
    
    always@(posedge clk)
        begin
            if(reset)
                state = A;
            else
                begin
                    if(state == A)
                        count = 2'b0;
                    else if(state == B)
                        count = w;
                    else
                        count = count + w;
                	state = next;
                end
        end
    
    always@(*)
        begin
            z = (state == B && count == 2);
        end
endmodule

自己写的在波形图不匹配，问题在于，希望在B状态进行复杂描述，反而出错。这里参考了CSDN上的一个写法。
CSDN网站

if(state == A)
                        count = 2'b0;
                    else if(state == B)
                        count = w;
                    else
                        count = count + w;
                	state = next;

这里的处理方法挺好的，是自己没有想到的，我是想用卡诺图实现，但没能成功。