Sequence recognition

//----------------way1----------------------
module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);

    parameter NONE = 4'd0,ONE = 4'd1,TWO = 4'd2;
    parameter THREE = 4'd3,FOUR = 4'd4,FIVE = 4'd5;
    parameter SIX = 4'd6,ERROR = 4'd7;
    parameter DISC = 4'd8,FLAG = 4'd9;

    reg [3:0] current_state,next_state;

    always @(*) begin
        case(current_state)
            NONE:begin
                next_state = in ? ONE : NONE;
            end
            ONE:begin
                next_state = in ? TWO : NONE;
            end
            TWO:begin
                next_state = in ? THREE : NONE;
            end
            THREE:begin
                next_state = in ? FOUR : NONE;
            end
            FOUR:begin
                next_state = in ? FIVE : NONE;
            end
            FIVE:begin
                next_state = in ? SIX : DISC;
            end
            SIX:begin
                next_state = in ? ERROR : FLAG;
            end
            DISC:begin
                next_state = in ? ONE : NONE;
            end
            FLAG:begin
                next_state = in ? ONE : NONE;
            end
            ERROR:begin
                next_state = in ? ERROR : NONE;
            end
        endcase
    end

    always @(posedge clk) begin
        if(reset)begin
            current_state <= NONE;
        end
        else begin
            current_state <= next_state;
        end
    end

    always @(posedge clk) begin
        if(reset)begin
            disc <= 1'd0;
            flag <= 1'd0;
            err  <= 1'd0;
        end
        else begin
            case(next_state)
                DISC:begin
                    disc <= 1'd1;
                    flag <= 1'd0;
                    err  <= 1'd0;
                end
                FLAG:begin
                    disc <= 1'd0;
                    flag <= 1'd1;
                    err  <= 1'd0;
                end
                ERROR:begin
                    disc <= 1'd0;
                    flag <= 1'd0;
                    err  <= 1'd1;
                end
                default:begin
                    disc <= 1'd0;
                    flag <= 1'd0;
                    err  <= 1'd0;
                end
            endcase
        end
    end

endmodule