Serial receiver and datapath

合集 - Verilog学习(62)

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39.Serial receiver and datapath2024-04-15

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See also: Serial receiver

Now that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don't-care otherwise.

Note that the serial protocol sends the least significant bit first.

题目网站

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
    
    parameter [3:0] START = 4'd0;
    parameter [3:0] ONE = 4'd1;
    parameter [3:0] TWO = 4'd2;
    parameter [3:0] THREE = 4'd3;
    parameter [3:0] FOUR = 4'd4;
    parameter [3:0] FIVE = 4'd5;
    parameter [3:0] SIX = 4'd6;
    parameter [3:0] SEVEN = 4'd7;
    parameter [3:0] EIGHT = 4'd8;
    parameter [3:0] STOP = 4'd9;
    parameter [3:0] IDLE = 4'd10;
    parameter [3:0] WAIT = 4'd11;
    
    reg [3:0] state,next_state;
    
    reg [7:0]	par_in;
    
    always @(*)begin
        case(state)
            START:begin
                next_state = ONE;
                par_in[0] = in;
            end
            ONE:begin
                next_state = TWO;
                par_in[1] = in;
            end
            TWO:begin
                next_state = THREE;
                par_in[2] = in;
            end
            THREE:begin
                next_state = FOUR;
                par_in[3] = in;
            end
            FOUR:begin
                next_state = FIVE;
                par_in[4] = in;
            end
            FIVE:begin
                next_state = SIX;
                par_in[5] = in;
            end
            SIX:begin
                next_state = SEVEN;
                par_in[6] = in;
            end
            SEVEN:begin
                next_state = EIGHT;
                par_in[7] = in;
            end
            EIGHT:begin
                if(in)begin
                    next_state = STOP;
                end
                else begin
                    next_state = WAIT;
                end
            end
            STOP:begin
                if(in)begin
                    next_state = IDLE;
                end
                else begin
                    next_state = START;
                end
            end
            WAIT:begin
                if(in)begin
                    next_state = IDLE;
                end
                else begin
                    next_state = WAIT;
                end
            end
            IDLE:begin
                if(~in)begin
                    next_state = START;
                end
                else begin
                    next_state = IDLE;
                end
            end
        endcase
    end
    
    always @(posedge clk)begin
        if(reset)begin
            state <= IDLE;
        end
        else begin
            state <= next_state;
        end
    end
    
    assign done = (state == STOP);
    assign out_byte = (state == STOP) ? par_in : 8'd0;

endmodule