Serial receiver

合集 - Verilog学习(62)

1.Decade counter2024-04-102.Four-bit binary counter2024-04-103.Decade counter again2024-04-104.Slow decade counter2024-04-105.Counter 1-122024-04-106.Counter 10002024-04-107.4-digit decimal counter2024-04-108.12-hour clock2024-04-109.Hdlbits博文分布2024-04-1010.4-bit shift register2024-04-1111.Left/right rotator2024-04-1112.Left/right arithmetic shift by 1 or 82024-04-1113.5-bit LFSR2024-04-1114.3-bit LFSR2024-04-1115.32-bit LFSR2024-04-1116.Shift register2024-04-1117.Shift register(2)2024-04-1118.3-input LUT2024-04-1119.Rule 902024-04-1220.Rule 1102024-04-1221.Conway's Game of Life 16x162024-04-1222.Simple FSM1(asynchronous reset)2024-04-1423.Simple FSM1(synchronous reset)2024-04-1424.Simple FSM2(asynchronous reset)2024-04-1425.Simple FSM2(synchronous reset)2024-04-1426.Simple state transition 32024-04-1427.Simple one-hot state transition 32024-04-1428.Simple FSM 3（asynchronous reset）2024-04-1429.Simple FSM 3（synchronous reset）2024-04-1430.Design a Moore FSM2024-04-1431.Lemmings 12024-04-1432.Lemmings 22024-04-1433.Lemmings 32024-04-1534.Lemmings 42024-04-1535.One-hot FSM2024-04-1536.PS/2 packet parser2024-04-1537.PS/2 packet parser and datapath2024-04-15

38.Serial receiver2024-04-15

39.Serial receiver and datapath2024-04-1540.Serial receiver with parity checking2024-04-1541.Sequence recognition2024-04-1642.Q8:Design a Mealy FSM2024-04-1643.Q5a:Serial two's complementer(Moore FSM)2024-04-1644.Q5b:Serial two's complementer(Moore FSM)2024-04-1645.Q3a:FSM2024-04-1646.Q3b:FSM2024-04-1647.Q3c:FSM logic2024-04-1648.Q6b:FSM next-state logic2024-04-1649.Q6c:FSM next-state logic2024-04-1650.Q6:FSM2024-04-1651.Q2a：FSM2024-04-1652.Q2:One-hot FSM equations2024-04-1653.Q2a: FSM2024-04-1654.Q2b：Another FSM2024-04-1655.Counter with period 10002024-04-1656.4-bit shift register and down counter2024-04-1657.FSM:Sequence 1101 recognizer2024-04-1658.FSM:Enable shift register2024-04-1659.FSM:The complete FSM2024-04-1660.The complete timer2024-04-1661.FSM:One-hot logic equations2024-04-1662.UART2024-04-16

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In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).

Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.

在许多（较旧的）串行通信协议中，每个数据字节都与起始位和停止位一起发送，以帮助接收方从位流中分隔字节。一种常见的方案是使用 1 个起始位 （0）、8 个数据位和 1 个停止位 （1）。当没有传输任何内容（空闲）时，该线路也处于逻辑 1 处。

设计一个有限状态机，当给定一个位流时，它将识别何时正确接收字节。它需要识别起始位，等待所有 8 个数据位，然后验证停止位是否正确。如果停止位未按预期出现，则 FSM 必须等到找到停止位后再尝试接收下一个字节。
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module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter [3:0] START = 4'd0;
    parameter [3:0] ONE = 4'd1;
    parameter [3:0] TWO = 4'd2;
    parameter [3:0] THREE = 4'd3;
    parameter [3:0] FOUR = 4'd4;
    parameter [3:0] FIVE = 4'd5;
    parameter [3:0] SIX = 4'd6;
    parameter [3:0] SEVEN = 4'd7;
    parameter [3:0] EIGHT = 4'd8;
    parameter [3:0] STOP = 4'd9;
    parameter [3:0] IDLE = 4'd10;
    parameter [3:0] WAIT = 4'd11;
    
    reg [3:0] state,next_state;
    
    always @(*)begin
        case(state)
            START:begin
                next_state = ONE;
            end
            ONE:begin
                next_state = TWO;
            end
            TWO:begin
                next_state = THREE;
            end
            THREE:begin
                next_state = FOUR;
            end
            FOUR:begin
                next_state = FIVE;
            end
            FIVE:begin
                next_state = SIX;
            end
            SIX:begin
                next_state = SEVEN;
            end
            SEVEN:begin
                next_state = EIGHT;
            end
            EIGHT:begin
                if(in)begin
                    next_state = STOP;
                end
                else begin
                    next_state = WAIT;
                end
            end
            STOP:begin
                if(in)begin
                    next_state = IDLE;
                end
                else begin
                    next_state = START;
                end
            end
            WAIT:begin
                if(in)begin
                    next_state = IDLE;
                end
                else begin
                    next_state = WAIT;
                end
            end
            IDLE:begin
                if(~in)begin
                    next_state = START;
                end
                else begin
                    next_state = IDLE;
                end
            end
        endcase
    end
    
    always @(posedge clk)begin
        if(reset)begin
            state <= IDLE;
        end
        else begin
            state <= next_state;
        end
    end
    
    assign done = (state == STOP);

endmodule