Serial receiver

In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).

Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.

在许多（较旧的）串行通信协议中，每个数据字节都与起始位和停止位一起发送，以帮助接收方从位流中分隔字节。一种常见的方案是使用 1 个起始位 （0）、8 个数据位和 1 个停止位 （1）。当没有传输任何内容（空闲）时，该线路也处于逻辑 1 处。

设计一个有限状态机，当给定一个位流时，它将识别何时正确接收字节。它需要识别起始位，等待所有 8 个数据位，然后验证停止位是否正确。如果停止位未按预期出现，则 FSM 必须等到找到停止位后再尝试接收下一个字节。
题目网站

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter [3:0] START = 4'd0;
    parameter [3:0] ONE = 4'd1;
    parameter [3:0] TWO = 4'd2;
    parameter [3:0] THREE = 4'd3;
    parameter [3:0] FOUR = 4'd4;
    parameter [3:0] FIVE = 4'd5;
    parameter [3:0] SIX = 4'd6;
    parameter [3:0] SEVEN = 4'd7;
    parameter [3:0] EIGHT = 4'd8;
    parameter [3:0] STOP = 4'd9;
    parameter [3:0] IDLE = 4'd10;
    parameter [3:0] WAIT = 4'd11;
    
    reg [3:0] state,next_state;
    
    always @(*)begin
        case(state)
            START:begin
                next_state = ONE;
            end
            ONE:begin
                next_state = TWO;
            end
            TWO:begin
                next_state = THREE;
            end
            THREE:begin
                next_state = FOUR;
            end
            FOUR:begin
                next_state = FIVE;
            end
            FIVE:begin
                next_state = SIX;
            end
            SIX:begin
                next_state = SEVEN;
            end
            SEVEN:begin
                next_state = EIGHT;
            end
            EIGHT:begin
                if(in)begin
                    next_state = STOP;
                end
                else begin
                    next_state = WAIT;
                end
            end
            STOP:begin
                if(in)begin
                    next_state = IDLE;
                end
                else begin
                    next_state = START;
                end
            end
            WAIT:begin
                if(in)begin
                    next_state = IDLE;
                end
                else begin
                    next_state = WAIT;
                end
            end
            IDLE:begin
                if(~in)begin
                    next_state = START;
                end
                else begin
                    next_state = IDLE;
                end
            end
        endcase
    end
    
    always @(posedge clk)begin
        if(reset)begin
            state <= IDLE;
        end
        else begin
            state <= next_state;
        end
    end
    
    assign done = (state == STOP);

endmodule