PS/2 packet parser and datapath

合集 - Verilog学习(62)

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37.PS/2 packet parser and datapath2024-04-15

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See also: PS/2 packet parser.

Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).

out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don't-care).

另请参阅：PS/2 数据包解析器。

现在，您已经拥有了一台状态机，该状态机将识别 PS/2 字节流中的三字节消息，请添加一个数据路径，该数据路径也将在收到数据包时输出 24 位（3 字节）消息（out_bytes[23：16] 是第一个字节，out_bytes[15：8] 是第二个字节，依此类推）。

每当断言完成信号时，out_bytes都需要有效。您可以在其他时间输出任何内容（即，不在乎）。
题目网站

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //

    parameter idle=4'b0001,
    		first=4'b0010,
    		second=4'b0100,
    		third=4'b1000;
    reg [3:0]state,nstate;
    
    always@(*)begin
        case(state)
            idle:begin
                if(in[3])begin
                    nstate=first;
                end
                else begin
                    nstate=idle;
                end
            end
            first:nstate=second;
            second:nstate=third;
            third:begin
                if(!in[3])begin
                    nstate=idle;
                end
                else begin
                    nstate=first;
                end
            end
        endcase
    end
    
    always@(posedge clk)begin
        if(reset)begin
            state<=idle;
        end
        else begin
            state<=nstate;
        end
    end
    
    reg [23:0]data;
    assign done=(state==third);
        always @(posedge clk) begin
        if (reset) begin
            data <= 24'd0;
        end
        else begin
            data[23:16] <= data[15:8];
            data[15:8] <= data[7:0];
            data[7:0]  <= in;
        end
    end

    assign out_bytes = (done) ? data : 24'd0;

endmodule

在上一题的基础上，增加一个数据流录入的模块