PS/2 packet parser

合集 - Verilog学习(62)

1.Decade counter2024-04-102.Four-bit binary counter2024-04-103.Decade counter again2024-04-104.Slow decade counter2024-04-105.Counter 1-122024-04-106.Counter 10002024-04-107.4-digit decimal counter2024-04-108.12-hour clock2024-04-109.Hdlbits博文分布2024-04-1010.4-bit shift register2024-04-1111.Left/right rotator2024-04-1112.Left/right arithmetic shift by 1 or 82024-04-1113.5-bit LFSR2024-04-1114.3-bit LFSR2024-04-1115.32-bit LFSR2024-04-1116.Shift register2024-04-1117.Shift register(2)2024-04-1118.3-input LUT2024-04-1119.Rule 902024-04-1220.Rule 1102024-04-1221.Conway's Game of Life 16x162024-04-1222.Simple FSM1(asynchronous reset)2024-04-1423.Simple FSM1(synchronous reset)2024-04-1424.Simple FSM2(asynchronous reset)2024-04-1425.Simple FSM2(synchronous reset)2024-04-1426.Simple state transition 32024-04-1427.Simple one-hot state transition 32024-04-1428.Simple FSM 3（asynchronous reset）2024-04-1429.Simple FSM 3（synchronous reset）2024-04-1430.Design a Moore FSM2024-04-1431.Lemmings 12024-04-1432.Lemmings 22024-04-1433.Lemmings 32024-04-1534.Lemmings 42024-04-1535.One-hot FSM2024-04-15

36.PS/2 packet parser2024-04-15

37.PS/2 packet parser and datapath2024-04-1538.Serial receiver2024-04-1539.Serial receiver and datapath2024-04-1540.Serial receiver with parity checking2024-04-1541.Sequence recognition2024-04-1642.Q8:Design a Mealy FSM2024-04-1643.Q5a:Serial two's complementer(Moore FSM)2024-04-1644.Q5b:Serial two's complementer(Moore FSM)2024-04-1645.Q3a:FSM2024-04-1646.Q3b:FSM2024-04-1647.Q3c:FSM logic2024-04-1648.Q6b:FSM next-state logic2024-04-1649.Q6c:FSM next-state logic2024-04-1650.Q6:FSM2024-04-1651.Q2a：FSM2024-04-1652.Q2:One-hot FSM equations2024-04-1653.Q2a: FSM2024-04-1654.Q2b：Another FSM2024-04-1655.Counter with period 10002024-04-1656.4-bit shift register and down counter2024-04-1657.FSM:Sequence 1101 recognizer2024-04-1658.FSM:Enable shift register2024-04-1659.FSM:The complete FSM2024-04-1660.The complete timer2024-04-1661.FSM:One-hot logic equations2024-04-1662.UART2024-04-16

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The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it's not obvious where messages start and end. The only indication is that the first byte of each three byte message always has bit[3]=1 (but bit[3] of the other two bytes may be 1 or 0 depending on data).

We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with bit[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done).

The FSM should signal done in the cycle immediately after the third byte of each message was successfully received.

PS/2 鼠标协议发送长度为 3 个字节的消息。但是，在连续的字节流中，消息的开始和结束位置并不明显。唯一的指示是，每三个字节消息的第一个字节始终具有 bit[3]=1（但其他两个字节的 bit[3] 可能是 1 或 0，具体取决于数据）。

我们想要一个有限状态机，当给定一个输入字节流时，它将搜索消息边界。我们将使用的算法是丢弃字节，直到我们看到一个 bit[3]=1 的字节。然后，我们假设这是消息的字节 1，并在收到所有 3 个字节（完成）后发出接收消息的信号。

FSM 应在成功接收到每条消息的第三个字节后立即在周期内发出信号。
题目网站
状态转换图如下：

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //

    parameter idle=4'b0001,
    		first=4'b0010,
    		second=4'b0100,
    		third=4'b1000;
    reg [3:0]state,nstate;
    
    always@(*)begin
        case(state)
            idle:begin
                if(in[3])begin
                    nstate=first;
                end
                else begin
                    nstate=idle;
                end
            end
            first:nstate=second;
            second:nstate=third;
            third:begin
                if(!in[3])begin
                    nstate=idle;
                end
                else begin
                    nstate=first;
                end
            end
        endcase
    end
    
    always@(posedge clk)begin
        if(reset)begin
            state<=idle;
        end
        else begin
            state<=nstate;
        end
    end
    
    assign done=(state==third);

endmodule

关键点：

1. 这道题的状态机要能画出来，理解题目含义
2. 这是一个数据流，是一个连续的，所以有一个循环存在，只要in[3]==1一直满足，就会一直循环下去，可以在计算机网络数据包的设计中使用