Lemmings 4

合集 - Verilog学习(62)

1.Decade counter2024-04-102.Four-bit binary counter2024-04-103.Decade counter again2024-04-104.Slow decade counter2024-04-105.Counter 1-122024-04-106.Counter 10002024-04-107.4-digit decimal counter2024-04-108.12-hour clock2024-04-109.Hdlbits博文分布2024-04-1010.4-bit shift register2024-04-1111.Left/right rotator2024-04-1112.Left/right arithmetic shift by 1 or 82024-04-1113.5-bit LFSR2024-04-1114.3-bit LFSR2024-04-1115.32-bit LFSR2024-04-1116.Shift register2024-04-1117.Shift register(2)2024-04-1118.3-input LUT2024-04-1119.Rule 902024-04-1220.Rule 1102024-04-1221.Conway's Game of Life 16x162024-04-1222.Simple FSM1(asynchronous reset)2024-04-1423.Simple FSM1(synchronous reset)2024-04-1424.Simple FSM2(asynchronous reset)2024-04-1425.Simple FSM2(synchronous reset)2024-04-1426.Simple state transition 32024-04-1427.Simple one-hot state transition 32024-04-1428.Simple FSM 3（asynchronous reset）2024-04-1429.Simple FSM 3（synchronous reset）2024-04-1430.Design a Moore FSM2024-04-1431.Lemmings 12024-04-1432.Lemmings 22024-04-1433.Lemmings 32024-04-15

34.Lemmings 42024-04-15

35.One-hot FSM2024-04-1536.PS/2 packet parser2024-04-1537.PS/2 packet parser and datapath2024-04-1538.Serial receiver2024-04-1539.Serial receiver and datapath2024-04-1540.Serial receiver with parity checking2024-04-1541.Sequence recognition2024-04-1642.Q8:Design a Mealy FSM2024-04-1643.Q5a:Serial two's complementer(Moore FSM)2024-04-1644.Q5b:Serial two's complementer(Moore FSM)2024-04-1645.Q3a:FSM2024-04-1646.Q3b:FSM2024-04-1647.Q3c:FSM logic2024-04-1648.Q6b:FSM next-state logic2024-04-1649.Q6c:FSM next-state logic2024-04-1650.Q6:FSM2024-04-1651.Q2a：FSM2024-04-1652.Q2:One-hot FSM equations2024-04-1653.Q2a: FSM2024-04-1654.Q2b：Another FSM2024-04-1655.Counter with period 10002024-04-1656.4-bit shift register and down counter2024-04-1657.FSM:Sequence 1101 recognizer2024-04-1658.FSM:Enable shift register2024-04-1659.FSM:The complete FSM2024-04-1660.The complete timer2024-04-1661.FSM:One-hot logic equations2024-04-1662.UART2024-04-16

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See also: Lemmings1, Lemmings2, and Lemmings3.

Although Lemmings can walk, fall, and dig, Lemmings aren't invulnerable. If a Lemming falls for too long then hits the ground, it can splatter. In particular, if a Lemming falls for more than 20 clock cycles then hits the ground, it will splatter and cease walking, falling, or digging (all 4 outputs become 0), forever (Or until the FSM gets reset). There is no upper limit on how far a Lemming can fall before hitting the ground. Lemmings only splatter when hitting the ground; they do not splatter in mid-air.

Extend your finite state machine to model this behaviour.

另请参阅：Lemmings1、Lemmings2 和 Lemmings3。

虽然旅鼠可以走路、跌倒和挖掘，但旅鼠并不是刀枪不入的。如果旅鼠跌倒时间过长然后撞到地面，它可能会飞溅。特别是，如果旅鼠跌倒超过 20 个时钟周期然后撞到地面，它会飞溅并停止行走、跌落或挖掘（所有 4 个输出变为 0），永远（或直到 FSM 被重置）。旅鼠在落地之前可以跌落多远没有上限。旅鼠只有在落地时才会飞溅;它们不会在半空中飞溅。

扩展有限状态机以对此行为进行建模。

跌倒 20 个周期是可以生存的：
题目网站

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
	parameter left=0,right=1,falll=2,fallr=3,digl=4,digr=5,die=6;
    reg [2:0] state,nstate;
    int counter;
   
   //状态交换 
    always @(posedge clk or posedge areset) begin
        if(areset) 
            state <= left;
        else 
            state <= nstate;
    end
    
    //计数器
    always @(posedge clk or posedge areset) begin
        if(areset)
            counter <= 0;
        else if(nstate==fallr||nstate==falll) begin
            counter <= counter+1;
        end
        else if(counter > 20)
            counter <= counter;
        else
            counter <= 0;
    end
    
    //下一个状态
    always @(*) begin
        case(state)
            left: nstate = ground?(dig?digl:(bump_left?right:left)):falll;
            right: nstate = ground?(dig?digr:(bump_right?left:right)):fallr;
            falll: nstate = ground?((counter>20)?die:left):falll;
            fallr: nstate = ground?((counter>20)?die:right):fallr;
            digl: nstate = ground?digl:falll;
            digr: nstate = ground?digr:fallr;
            die: nstate = die;
            default: nstate = 3'bx;
        endcase
    end
    
    //状态输出
    assign walk_left = (state == left)&&!(state == die);
    assign walk_right = (state == right)&&!(state == die);
    assign aaah = (state == fallr)||(state == falll)&&!(state == die);
    assign digging = (state == digr)||(state == digl)&&!(state == die);
endmodule