Lemmings 3

合集 - Verilog学习(62)

1.Decade counter2024-04-102.Four-bit binary counter2024-04-103.Decade counter again2024-04-104.Slow decade counter2024-04-105.Counter 1-122024-04-106.Counter 10002024-04-107.4-digit decimal counter2024-04-108.12-hour clock2024-04-109.Hdlbits博文分布2024-04-1010.4-bit shift register2024-04-1111.Left/right rotator2024-04-1112.Left/right arithmetic shift by 1 or 82024-04-1113.5-bit LFSR2024-04-1114.3-bit LFSR2024-04-1115.32-bit LFSR2024-04-1116.Shift register2024-04-1117.Shift register(2)2024-04-1118.3-input LUT2024-04-1119.Rule 902024-04-1220.Rule 1102024-04-1221.Conway's Game of Life 16x162024-04-1222.Simple FSM1(asynchronous reset)2024-04-1423.Simple FSM1(synchronous reset)2024-04-1424.Simple FSM2(asynchronous reset)2024-04-1425.Simple FSM2(synchronous reset)2024-04-1426.Simple state transition 32024-04-1427.Simple one-hot state transition 32024-04-1428.Simple FSM 3（asynchronous reset）2024-04-1429.Simple FSM 3（synchronous reset）2024-04-1430.Design a Moore FSM2024-04-1431.Lemmings 12024-04-1432.Lemmings 22024-04-14

33.Lemmings 32024-04-15

34.Lemmings 42024-04-1535.One-hot FSM2024-04-1536.PS/2 packet parser2024-04-1537.PS/2 packet parser and datapath2024-04-1538.Serial receiver2024-04-1539.Serial receiver and datapath2024-04-1540.Serial receiver with parity checking2024-04-1541.Sequence recognition2024-04-1642.Q8:Design a Mealy FSM2024-04-1643.Q5a:Serial two's complementer(Moore FSM)2024-04-1644.Q5b:Serial two's complementer(Moore FSM)2024-04-1645.Q3a:FSM2024-04-1646.Q3b:FSM2024-04-1647.Q3c:FSM logic2024-04-1648.Q6b:FSM next-state logic2024-04-1649.Q6c:FSM next-state logic2024-04-1650.Q6:FSM2024-04-1651.Q2a：FSM2024-04-1652.Q2:One-hot FSM equations2024-04-1653.Q2a: FSM2024-04-1654.Q2b：Another FSM2024-04-1655.Counter with period 10002024-04-1656.4-bit shift register and down counter2024-04-1657.FSM:Sequence 1101 recognizer2024-04-1658.FSM:Enable shift register2024-04-1659.FSM:The complete FSM2024-04-1660.The complete timer2024-04-1661.FSM:One-hot logic equations2024-04-1662.UART2024-04-16

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See also: Lemmings1 and Lemmings2.

In addition to walking and falling, Lemmings can sometimes be told to do useful things, like dig (it starts digging when dig=1). A Lemming can dig if it is currently walking on ground (ground=1 and not falling), and will continue digging until it reaches the other side (ground=0). At that point, since there is no ground, it will fall (aaah!), then continue walking in its original direction once it hits ground again. As with falling, being bumped while digging has no effect, and being told to dig when falling or when there is no ground is ignored.

(In other words, a walking Lemming can fall, dig, or switch directions. If more than one of these conditions are satisfied, fall has higher precedence than dig, which has higher precedence than switching directions.)

参见：Lemmings1 和 Lemmings2。

除了走路和跌倒之外，旅鼠有时还可以被告知做一些有用的事情，比如挖掘（当 dig=1 时它开始挖掘）。如果旅鼠目前在地面上行走（地面=1且没有坠落），则可以挖掘，并将继续挖掘，直到到达另一侧（地面=0）。在这一点上，由于没有地面，它会掉下来（啊！），然后在它再次落地后继续向原来的方向行走。与跌倒一样，在挖掘时被撞到是没有效果的，在跌倒或没有地面时被告知挖掘是被忽略的。

（换句话说，行走的旅鼠可以跌倒、挖掘或改变方向。如果满足这些条件中的多个条件，则 fall 的优先级高于 dig，而 dig 的优先级高于切换方向的优先级。

扩展有限状态机以对此行为进行建模。
题目网站
状态转换如下：

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
 
    parameter LEFT=6'b000_001,
    		  RIGHT=6'b000_010,
    		  FALL_L=6'b000_100,
    		  FALL_R=6'b001_000,
    		  DIG_L=6'b010_000,
    		  DIG_R=6'b100_000;
    reg [5:0]state,nstate;
    reg [3:0]judge;
    assign judge={ground,dig,bump_left,bump_right};
    
    always@(*)begin
        case(state)
            LEFT:begin
                casex(judge)
                    4'b0xxx:nstate=FALL_L;
                    4'b11xx:nstate=DIG_L;
                    4'b101x:nstate=RIGHT;
                    default:nstate=LEFT;
                endcase
            end
            RIGHT:begin
                casex(judge)
                    4'b0xxx:nstate=FALL_R;
                    4'b11xx:nstate=DIG_R;
                    4'b1001:nstate=LEFT;
                    default:nstate=RIGHT;
                endcase
            end
            FALL_L:begin
                casex(judge)
                    4'b1xxx:nstate=LEFT;
                    default:nstate=FALL_L;
                endcase
            end
            FALL_R:begin
                casex(judge)
                    4'b1xxx:nstate=RIGHT;
                    default:nstate=FALL_R;
                endcase
            end
            DIG_L:begin
                casex(judge)
                    4'b0xxx:nstate=FALL_L;
                    default:nstate=DIG_L;
                endcase
            end
            DIG_R:begin
                casex(judge)
                    4'b0xxx:nstate=FALL_R;
                    default:nstate=DIG_R;
                endcase
            end
        endcase
    end
    
    always@(posedge clk or posedge areset)begin
        if(areset)begin
            state<=LEFT;
        end
        else begin
            state<=nstate;
        end
    end
    
    assign walk_left=(state==LEFT);
    assign walk_right=(state==RIGHT);
    assign digging=(state==DIG_L||state==DIG_R);
    assign aaah=(state==FALL_L||state==FALL_R);
            
endmodule

完美，终于可以完全自己写出来了，理解了逻辑就好办了