Lemmings 2

合集 - Verilog学习(62)

1.Decade counter2024-04-102.Four-bit binary counter2024-04-103.Decade counter again2024-04-104.Slow decade counter2024-04-105.Counter 1-122024-04-106.Counter 10002024-04-107.4-digit decimal counter2024-04-108.12-hour clock2024-04-109.Hdlbits博文分布2024-04-1010.4-bit shift register2024-04-1111.Left/right rotator2024-04-1112.Left/right arithmetic shift by 1 or 82024-04-1113.5-bit LFSR2024-04-1114.3-bit LFSR2024-04-1115.32-bit LFSR2024-04-1116.Shift register2024-04-1117.Shift register(2)2024-04-1118.3-input LUT2024-04-1119.Rule 902024-04-1220.Rule 1102024-04-1221.Conway's Game of Life 16x162024-04-1222.Simple FSM1(asynchronous reset)2024-04-1423.Simple FSM1(synchronous reset)2024-04-1424.Simple FSM2(asynchronous reset)2024-04-1425.Simple FSM2(synchronous reset)2024-04-1426.Simple state transition 32024-04-1427.Simple one-hot state transition 32024-04-1428.Simple FSM 3（asynchronous reset）2024-04-1429.Simple FSM 3（synchronous reset）2024-04-1430.Design a Moore FSM2024-04-1431.Lemmings 12024-04-14

32.Lemmings 22024-04-14

33.Lemmings 32024-04-1534.Lemmings 42024-04-1535.One-hot FSM2024-04-1536.PS/2 packet parser2024-04-1537.PS/2 packet parser and datapath2024-04-1538.Serial receiver2024-04-1539.Serial receiver and datapath2024-04-1540.Serial receiver with parity checking2024-04-1541.Sequence recognition2024-04-1642.Q8:Design a Mealy FSM2024-04-1643.Q5a:Serial two's complementer(Moore FSM)2024-04-1644.Q5b:Serial two's complementer(Moore FSM)2024-04-1645.Q3a:FSM2024-04-1646.Q3b:FSM2024-04-1647.Q3c:FSM logic2024-04-1648.Q6b:FSM next-state logic2024-04-1649.Q6c:FSM next-state logic2024-04-1650.Q6:FSM2024-04-1651.Q2a：FSM2024-04-1652.Q2:One-hot FSM equations2024-04-1653.Q2a: FSM2024-04-1654.Q2b：Another FSM2024-04-1655.Counter with period 10002024-04-1656.4-bit shift register and down counter2024-04-1657.FSM:Sequence 1101 recognizer2024-04-1658.FSM:Enable shift register2024-04-1659.FSM:The complete FSM2024-04-1660.The complete timer2024-04-1661.FSM:One-hot logic equations2024-04-1662.UART2024-04-16

收起

See also: Lemmings1.

In addition to walking left and right, Lemmings will fall (and presumably go "aaah!") if the ground disappears underneath them.

In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say "aaah!". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.

Build a finite state machine that models this behaviour.

参见：旅鼠1。

除了向左和向右走之外，如果下面的地面消失，旅鼠还会摔倒（大概会“啊啊！”）。

除了左右行走和撞到时改变方向外，当地面=0时，旅鼠还会摔倒并说“啊！当地面重新出现（地面=1）时，旅鼠将恢复与坠落前相同的方向行走。跌倒时被撞不会影响行走方向，与地面消失（但尚未跌倒）相同的周期被撞，或者地面在跌倒时重新出现时，也不会影响行走方向。

构建一个有限状态机来模拟这种行为。
题目网站

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 

    parameter LEFT=2'b00,RIGHT=2'b01,LEFT_F=2'b10,RIGHT_F=2'b11;
    reg [3:0]state,next_state;
    wire [1:0]bump;
    assign bump={bump_left,bump_right};
    
    always@(*)begin
        case(state)
            LEFT:begin
                if(ground==1'b0)begin
                    next_state=LEFT_F;
                end
                else if(ground==1'b1)begin
                    if(bump==2'b11||bump==2'b10)begin
                    next_state=RIGHT;
                	end
                	else begin
                    next_state=LEFT;
                	end
                end
            end
            RIGHT:begin
                if(ground==1'b0)begin
                    next_state=RIGHT_F;
                end
                else if(ground==1'b1)begin
                    if(bump==2'b11||bump==2'b01)begin
                    next_state=LEFT;
                	end
                	else begin
                    next_state=RIGHT;
                	end
                end
            end
            LEFT_F:begin
                if(ground==1'b0)begin
                    next_state=LEFT_F;
                end
                else if(ground==1'b1)begin
                    next_state=LEFT;
                end
            end
            RIGHT_F:begin
                if(ground==1'b0)begin
                    next_state=RIGHT_F;
                end
                else if(ground==1'b1)begin
                    next_state=RIGHT;
                end
            end
        endcase
    end
    
    always@(posedge clk,posedge areset)begin
        if(areset)begin
            state<=LEFT;
        end
        else begin
            state<=next_state;
        end
    end
    
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT); 
    assign aaah=(state==LEFT_F||state==RIGHT_F);
    
endmodule

这个题目如果有状态机图，会好些很多，因为实现的方法有很多种。
自己的写法在波形图中总是有一条不匹配，所以借鉴了这个写法
CSDN写法

另外，开始逐渐复杂的状态转换图也让我想去找到一款高效的状态转换绘图软件，暂时找到了如下：
一款用于绘制状态机转换图和流程图的web在线绘图工具
有时间的话，会再做一次详细的介绍和尝试