Simple FSM1(synchronous reset)

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1, but using synchronous reset.

题目网站

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;
	parameter A=0,B=1;
    // Fill in state name declarations
    reg present_state, next_state;
    always @(posedge clk) begin
        if (reset) begin  
            // Fill in reset logic
            present_state<=B;
            out<=1'b1;
        end
        else begin
            case (present_state)
                // Fill in state transition logic
                A:begin
                    if(in)begin
                        present_state<=A;
                        out<=1'b0;
                        //present_state<=next_state;
                    end
                    else begin
                        present_state<=B;
                        out<=1'b1;
                        //present_state<=next_state;
                    end
                end
                B:begin
                    if(in)begin
                        present_state<=B;
                        out<=1'b1;
                        //present_state<=next_state;
                    end
                    else begin
                        present_state<=A;
                        out<=1'b0;
                        //present_state<=next_state;
                    end
                end
            endcase
        end
    end

endmodule

两段式写法配上同步复位