Rule 90
1.Decade counter2.Four-bit binary counter3.Decade counter again4.Slow decade counter5.Counter 1-126.Counter 10007.4-digit decimal counter8.12-hour clock9.Hdlbits博文分布10.4-bit shift register11.Left/right rotator12.Left/right arithmetic shift by 1 or 813.5-bit LFSR14.3-bit LFSR15.32-bit LFSR16.Shift register17.Shift register(2)18.3-input LUT
19.Rule 90
20.Rule 11021.Conway's Game of Life 16x1622.Simple FSM1(asynchronous reset)23.Simple FSM1(synchronous reset)24.Simple FSM2(asynchronous reset)25.Simple FSM2(synchronous reset)26.Simple state transition 327.Simple one-hot state transition 328.Simple FSM 3（asynchronous reset）29.Simple FSM 3（synchronous reset）30.Design a Moore FSM31.Lemmings 132.Lemmings 233.Lemmings 334.Lemmings 435.One-hot FSM36.PS/2 packet parser37.PS/2 packet parser and datapath38.Serial receiver39.Serial receiver and datapath40.Serial receiver with parity checking41.Sequence recognition42.Q8:Design a Mealy FSM43.Q5a:Serial two's complementer(Moore FSM)44.Q5b:Serial two's complementer(Moore FSM)45.Q3a:FSM46.Q3b:FSM47.Q3c:FSM logic48.Q6b:FSM next-state logic49.Q6c:FSM next-state logic50.Q6:FSM51.Q2a：FSM52.Q2:One-hot FSM equations53.Q2a: FSM54.Q2b：Another FSM55.Counter with period 100056.4-bit shift register and down counter57.FSM:Sequence 1101 recognizer58.FSM:Enable shift register59.FSM:The complete FSM60.The complete timer61.FSM:One-hot logic equations62.UARTRule 90 is a one-dimensional cellular automaton with interesting properties.
The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell's two current neighbours. A more verbose way of expressing this rule is the following table, where a cell's next state is a function of itself and its two neighbours:
规则 90 是一个具有有趣属性的一维元胞自动机。
规则很简单。有一个一维单元格数组（打开或关闭）。在每个时间步中，每个单元的下一个状态是单元的两个当前邻居的异或。下表是表达此规则的更详细的方式，其中单元格的下一个状态是其自身及其两个相邻单元的函数：
题目网站
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q );
integer i;
always@(posedge clk)begin
if(load)begin
q<=data;
end
else begin
q<={1'b0,q[511:1]}^{q[510:0],1'b0};
end
end
endmodule
这个写法画一个图方便理解，是从整体出发的写法：
从这个图可以看出q<={1'b0,q[511:1]}^{q[510:0],1'b0};中第一位0b就是原数列a的左右两位的异或，第二位ac就是原数列b的左右两位的异或……依此类推可得。
下面提供另一种写法：
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q );
always @(posedge clk ) begin
if(load)begin
q <= data;
end
else begin
q <= (q<<1)^(q>>1);
end
end
endmodule
这个写法用q <= (q<<1)^(q>>1);，写的更直观。
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