Shift register

Implement the following circuit:

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module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    reg [3:0]q;
    assign out=q[3];
    always@(posedge clk)begin
        if(!resetn)begin
            q<=4'b0;
        end
        else begin
            q[3]<=q[2];
            q[2]<=q[1];
            q[1]<=q[0];
            q[0]<=in;
        end
    end
            
endmodule