3-bit LFSR

合集 - Verilog学习(62)

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收起

Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the R inputs to the SW switches, connect Clock to KEY[0], and L to KEY[1]. Connect the Q outputs to the red lights LEDR.

为此时序电路编写Verilog代码（子模块可以，但顶层必须命名为top_module）。假设您要在 DE1-SoC 板上实现该电路。将 R 输入连接到 SW 开关，将 Clock 连接到 KEY[0]，将 L 连接到 KEY[1]。将 Q 输出连接到红灯 LEDR。

题目网站

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q

    wire clk;
    assign clk = KEY[0];
    
    always @(posedge clk)begin
        if(KEY[1])begin
            LEDR[0] <= SW[0];
            LEDR[1] <= SW[1];
            LEDR[2] <= SW[2];
        end
        else begin
            LEDR[0] <= LEDR[2];
            LEDR[1] <= LEDR[0];
            LEDR[2] <= LEDR[2] ^ LEDR[1];
        end
    end

endmodule

再写：
首先是对上述写法的理解：
其实就是三个D触发器，只不过在d段对输入进行一个二分之一的选择，情况较为简单，可以直接将二分之一选择并入D触发器的代码
而且因为三个D触发器的选择都是由L来控制，所以可以一下控制三个，也即：

        if(KEY[1])begin
            LEDR[0] <= SW[0];
            LEDR[1] <= SW[1];
            LEDR[2] <= SW[2];

然后再提供一种先写子模块，然后实例化的写法，如下：

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
    wire d21;
    assign d21=LEDR[1]^LEDR[2];
    
    little littleq0(.clk(KEY[0]),.d1(LEDR[2]),.d2(SW[0]),.l(KEY[1]),.q(LEDR[0]));
    little littleq1(.clk(KEY[0]),.d1(LEDR[0]),.d2(SW[1]),.l(KEY[1]),.q(LEDR[1]));
    little littleq2(.clk(KEY[0]),.d1(d21),.d2(SW[2]),.l(KEY[1]),.q(LEDR[2]));

endmodule

module little(
	input clk,
	input d1,
	input d2,
	input l,
    output q);
    wire d;
    assign d=(l)?d2:d1;
    always@(posedge clk)begin
        q<=d;
    end
endmodule

我自己的写法在命名上有些杂乱，但是只要抓住几个关键点即可：

1. input [1:0] KEY, // L and clk意思是L用KEY[0]，clk用KEY[1]表示
2. 线稍微有些多，理清楚