Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this case) instead of zero as done by a logical right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed and preserves the sign, so that arithmetic right shift divides a signed number by a power of two.
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1 module top_module(
2 input clk,
3 input load,
4 input ena,
5 input [1:0] amount,
6 input [63:0] data,
7 output reg [63:0] q);
8 always @(posedge clk)begin
9 if(load)begin
10 q <= data;
11 end
12 else begin
13 if(ena)begin //判断是否要移位
14 case(amount) //用case将几种情况分别说明
15 2'b00: q <= {q[62:0],1'b0};
16 2'b01: q <= {q[55:0],8'b0};
17 2'b10: q <= {q[63],q[63:1]};
18 2'b11: q <= {{8{q[63]}},q[63:8]};
19 endcase
20 end
21 else begin
22 q <= q;
23 end
24 end
25 end
26
27 endmodule
