Counter 1000
1.Decade counter2.Four-bit binary counter3.Decade counter again4.Slow decade counter5.Counter 1-12
6.Counter 1000
7.4-digit decimal counter8.12-hour clock9.Hdlbits博文分布10.4-bit shift register11.Left/right rotator12.Left/right arithmetic shift by 1 or 813.5-bit LFSR14.3-bit LFSR15.32-bit LFSR16.Shift register17.Shift register(2)18.3-input LUT19.Rule 9020.Rule 11021.Conway's Game of Life 16x1622.Simple FSM1(asynchronous reset)23.Simple FSM1(synchronous reset)24.Simple FSM2(asynchronous reset)25.Simple FSM2(synchronous reset)26.Simple state transition 327.Simple one-hot state transition 328.Simple FSM 3(asynchronous reset)29.Simple FSM 3(synchronous reset)30.Design a Moore FSM31.Lemmings 132.Lemmings 233.Lemmings 334.Lemmings 435.One-hot FSM36.PS/2 packet parser37.PS/2 packet parser and datapath38.Serial receiver39.Serial receiver and datapath40.Serial receiver with parity checking41.Sequence recognition42.Q8:Design a Mealy FSM43.Q5a:Serial two's complementer(Moore FSM)44.Q5b:Serial two's complementer(Moore FSM)45.Q3a:FSM46.Q3b:FSM47.Q3c:FSM logic48.Q6b:FSM next-state logic49.Q6c:FSM next-state logic50.Q6:FSM51.Q2a:FSM52.Q2:One-hot FSM equations53.Q2a: FSM54.Q2b:Another FSM55.Counter with period 100056.4-bit shift register and down counter57.FSM:Sequence 1101 recognizer58.FSM:Enable shift register59.FSM:The complete FSM60.The complete timer61.FSM:One-hot logic equations62.UARTFrom a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).
The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.
module bcdcount (
input clk,
input reset,
input enable,
output reg [3:0] Q
);
1 module top_module (
2 input clk,
3 input reset,
4 output OneHertz,
5 output [2:0] c_enable
6 ); //
7 wire[3:0] one, ten, hundred;
8 assign c_enable = {one == 4'd9 && ten == 4'd9, one == 4'd9, 1'b1};
9
10 assign OneHertz = (one == 4'd9 && ten == 4'd9 && hundred == 4'd9);
11
12 bcdcount counter0 (clk, reset, c_enable[0], one);
13 bcdcount counter1 (clk, reset, c_enable[1], ten);
14 bcdcount counter2 (clk, reset, c_enable[2], hundred);
15
16 //bcdcount counter0 (clk, reset, c_enable[0]/*, ... */);
17 //bcdcount counter1 (clk, reset, c_enable[1]/*, ... */);
18
19 endmodule
再写:
assign c_enable = {one == 4'd9 && ten == 4'd9, one == 4'd9, 1'b1};
的理解。
答:首先要理解c_enable
的作用,可以理解为这个计数器的小时、分钟、秒,这三个部分,每一个部分想启动一次计数,都要有这部分对应的enable
来作为使能信号。联系现实生活的时间计数(只不过这里是10倍10倍的计数,而不是60),秒的部分自然是每个周期都要运作,分钟的部分要在第10个周期,也即one == 4'd9
,小时的部分要在第100个周期,也即one == 4'd9 && ten == 4'd9
,因为调用的是bcd计数器,记不到100,只能10x10的来计数。
assign OneHertz = (one == 4'd9 && ten == 4'd9 && hundred == 4'd9);
的理解。
答:实现了“从 1000 Hz 时钟中,导出一个 1 Hz 信号,称为 OneHertz”的功能。
合集:
Verilog学习
【推荐】国内首个AI IDE,深度理解中文开发场景,立即下载体验Trae
【推荐】编程新体验,更懂你的AI,立即体验豆包MarsCode编程助手
【推荐】抖音旗下AI助手豆包,你的智能百科全书,全免费不限次数
【推荐】轻量又高性能的 SSH 工具 IShell:AI 加持,快人一步
· winform 绘制太阳,地球,月球 运作规律
· 震惊!C++程序真的从main开始吗?99%的程序员都答错了
· AI与.NET技术实操系列(五):向量存储与相似性搜索在 .NET 中的实现
· 超详细:普通电脑也行Windows部署deepseek R1训练数据并当服务器共享给他人
· 【硬核科普】Trae如何「偷看」你的代码?零基础破解AI编程运行原理