Decade counter
1.Decade counter
2.Four-bit binary counter3.Decade counter again4.Slow decade counter5.Counter 1-126.Counter 10007.4-digit decimal counter8.12-hour clock9.Hdlbits博文分布10.4-bit shift register11.Left/right rotator12.Left/right arithmetic shift by 1 or 813.5-bit LFSR14.3-bit LFSR15.32-bit LFSR16.Shift register17.Shift register(2)18.3-input LUT19.Rule 9020.Rule 11021.Conway's Game of Life 16x1622.Simple FSM1(asynchronous reset)23.Simple FSM1(synchronous reset)24.Simple FSM2(asynchronous reset)25.Simple FSM2(synchronous reset)26.Simple state transition 327.Simple one-hot state transition 328.Simple FSM 3（asynchronous reset）29.Simple FSM 3（synchronous reset）30.Design a Moore FSM31.Lemmings 132.Lemmings 233.Lemmings 334.Lemmings 435.One-hot FSM36.PS/2 packet parser37.PS/2 packet parser and datapath38.Serial receiver39.Serial receiver and datapath40.Serial receiver with parity checking41.Sequence recognition42.Q8:Design a Mealy FSM43.Q5a:Serial two's complementer(Moore FSM)44.Q5b:Serial two's complementer(Moore FSM)45.Q3a:FSM46.Q3b:FSM47.Q3c:FSM logic48.Q6b:FSM next-state logic49.Q6c:FSM next-state logic50.Q6:FSM51.Q2a：FSM52.Q2:One-hot FSM equations53.Q2a: FSM54.Q2b：Another FSM55.Counter with period 100056.4-bit shift register and down counter57.FSM:Sequence 1101 recognizer58.FSM:Enable shift register59.FSM:The complete FSM60.The complete timer61.FSM:One-hot logic equations62.UARTBuild a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.
1 module top_module (
2 input clk,
3 input reset, // Synchronous active-high reset
4 output [3:0] q);
5 always @(posedge clk)begin
6 if(reset || q >= 4'd9)begin //这里是什么意思?
7 q<=4'b0;
8 end
9 else begin
10 q<=q+1'b1;
11 end
12 end
13
14 endmodule
再写：
构建一个十进制计数器，从0-9，循环
对于注释“if(reset || q >= 4'd9)begin //这里是什么意思?”，这里等于是将两种情况，一个是重置，一个是循环到头，两者一起写了
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
always@(posedge clk)begin
if(reset)begin
q<=0;
end
else begin
if(q==4'd9)begin
q<=0;
end
else begin
q<=q+1'b1;
end
end
end
endmodule
合集:
Verilog学习
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