基于SparkRoad的Hdlbits学习（12）
input sel,
input [7:0] a,
input [7:0] b,
output [7:0]out );
assign out = sel?a:b;
endmodule
1.数据out的位宽不对
2.二选一的代码写法并不对assign out = (~sel & a) | (sel & b)
B站上提供了一种思路
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0]out );
assign out = ( {8{~sel}} & a ) | ( {8{sel}} & b ) ;
endmodule
但是也是编译不正确，为什么？
https://www.bilibili.com/read/cv16993094
NAND
module top_module (input a, input b, input c, output out);//
wire out_1;
andgate inst1 ( out_1,a,b, c ,1,1);
assign out=~out_1;
endmodule
1.要注意题目翻译，提供的是五门与模块
2.在调用模块的时候原先自己使用的是.out(out)这种形式，但不知道为什么不对
Mux
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out ); //
wire [7:0]mux00, mux11,mux22;
mux2 mux0 ( sel[0], a, b, mux00 );
mux2 mux1 ( sel[0], c, d, mux11 );
mux2 mux2 ( sel[1], mux00, mux11, out );
endmodule
1.对于模块的调用还不是很熟，以及调用模块后的命名
Add/sub
// synthesis verilog_input_version verilog_2001
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);//
always @(*) begin
case (do_sub)
0: out = a+b;
1: out = a-b;
endcase
if (out== 8'b0)
result_is_zero = 1;
else
result_is_zero = 0;
end
endmodule
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid);//
always @(*) begin
case (code)
8'h45: out = 4'd0;
8'h16: out = 4'd1;
8'h1e: out = 4'd2;
8'h26: out = 4'd3;
8'h25: out = 4'd4;
8'h2e: out = 4'd5;
8'h36: out = 4'd6;
8'h3d: out = 4'd7;
8'h3e: out = 4'd8;
8'h46: out = 4'd9;
default: begin
out = 4'd0;
end
endcase
if(out == 4'd0 && code!= 8'h45) begin
valid = 1'b0;
end
else begin
valid = 1'b1;
end
end
endmodule
默认输出valid=1不能按上图所示的编写代码，默认的输入可以；其次进制8'd26需改成8进制
Combinational circuit 1
module top_module (
input a,
input b,
output q );//
assign q = a & b;
endmodule
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = (~a&~b&~c&~d) | (~a&~b&c&d) | (~a&b&~c&d) | ~a&b&c&~d | a&~b&~c&d | a&~b&c&~d | a&b&~c&~d | a&b&c&d;
endmodule
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = b&d | a&d | b&c | a&c;
endmodule
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = b|c;
endmodule
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q );
always @(*) begin
case(c)
4'b0000: q = b;
4'b0001: q = e;
4'b0010: q = a;
4'b0011: q = d;
default: q = 4'hf;
endcase
end
endmodule
module top_module (
input [2:0] a,
output [15:0] q );
always @(*) begin
case (a)
0: q = 16'h1232;
1: q = 16'haee0;
2: q = 16'h27d4;
3: q = 16'h5a0e;
4: q = 16'h2066;
5: q = 16'h64ce;
6: q = 16'hc526;
7: q = 16'h2f19;
endcase
end
endmodule
module top_module (
input clk,
input a,
output q );
always @(posedge clk) begin
q <= ~a; //因为时序逻辑电路要延迟一个周期
end
endmodule
module top_module (
input clock,
input a,
output p,
output q );
always @(*) begin
if (clock)
p = a;
end
always @(negedge clock) begin
q <= p; //从这个题可以体现出组合和时序逻辑的区别，时序逻辑打一拍输出
end
endmodule
module top_module (
input clk,
input a,
output [3:0] q );
always @(posedge clk) begin
if (a)
q <= 4'd4;
else if(q<6)
q <= q + 4'd1;
else
q <= 4'd0;
end
endmodule
module top_module (
input clk,
input a,
input b,
output q,
output state );
always @(posedge clk) begin
if(a == b)
state <= a;
else
state <= state;
end
assign q = (a == b) ? state : (~state);
endmodule
module top_module ( );
parameter time_period = 10;
reg clk;
initial clk = 0;
always begin
#(time_period / 2) clk = ~clk;
end
dut dut1(clk);
endmodule
module top_module ( output reg A, output reg B );//
// generate input patterns here
initial begin
A = 0;
B = 0;
#10 A = 1;
#5 B = 1;
#5 A = 0;
#20 B = 0;
end
endmodule
module top_module();
reg [1:0] in;
reg out;
initial begin
in = 2'b00;
#10 in = 2'b01;
#10 in = 2'b10;
#10 in = 2'b11;
end
andgate gate1(in, out);
endmodule
module top_module();
reg clk;
reg in;
reg [2:0] s;
reg out;
initial begin
clk = 0;
in = 0;
s = 2;
#10 s = 6;
#10 begin
s = 2;
in = 1;
end
#10 begin
s = 7;
in = 0;
end
#10 begin
s = 0;
in = 1;
end
#30 in = 0;
end
always begin
#5 clk = ~clk;
end
q7 q71(clk, in, s, out);
endmodule
module top_module ();
reg clk;
reg reset;
reg t;
reg q;
initial begin
clk = 0;
reset = 0;
t = 0;
#15 reset = 1;
#10 reset = 0;
#10 t = 1;
end
always begin
#5 clk = ~clk;
end
tff tff1(clk, reset, t, q);
endmodule
