基于SparkRoad的Hdlbits学习（5）

学习：

Wire

module top_module (
    input in,
    output out);
	assign out=in;
endmodule

GND

module top_module (
    output out);
	assign out=1'b0;
endmodule

NOR

module top_module (
    input in1,
    input in2,
    output out);
    assign out=~(in1|in2);
endmodule

Another gate

module top_module (
    input in1,
    input in2,
    output out);
    assign out=in1&(~in2);
endmodule

Two gates

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
	wire in4;
    assign in4=~in1^in2;
    assign out=in4^in3;
endmodule

More logic gates

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
	assign out_and=a&b;
    assign out_or=a|b;
    assign out_xor=a^b;
    assign out_nand=~(a&b);
    assign out_nor=~(a|b);
    assign out_xnor=~(a^b);
    assign out_anotb=a & (~b);
endmodule

7420 chip

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign p1y=~(p1a&p1b&p1c&p1d);
    assign p2y=~(p2a&p2b&p2c&p2d);

endmodule

Truth tables

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);
    always@*begin
    case({x3,x2,x1})
        3'b000,3'b001,3'b100,3'b110:f=0;
        3'b010,3'b011,3'b101,3'b111:f=1;
    endcase
    end
endmodule

Two-bit equality

module top_module ( input [1:0] A, input [1:0] B, output z ); 
	assign z=(A==B)?1'b1:1'b0;
endmodule

Simple circuit A

module top_module (input x, input y, output z);
    assign z=(x^y)&x;
endmodule

Simple circuit B

module top_module ( input x, input y, output z );
    assign z=~(x^y);
endmodule

Combine circuits A and B

module top_module (input x, input y, output z);
    wire za;   // 这是结合了之前的两道题的小模块
    wire zb;
    
    assign za = (x ^ y) & x;
    assign zb = ~(x ^ y);
    assign z = (za | zb) ^ (za & zb);
endmodule

Ring or vibrate?

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
	assign motor=ring&vibrate_mode;
    assign ringer=ring&(~vibrate_mode);
endmodule

Thermostat

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
    /*if(mode==1'b1)begin
        if(too_cold==1'b1)begin
            assign heater=1'b1;
            assign aircon=1'b0;
            assign fan_on=1'b1;
        end
        else
            assign heater=1'b0;
    end
    else begin
        if(too_hot==1'b1)begin
            assign heater=1'b0;
            assign aircon=1'b1;
            assign fan_on=1'b1;
        end
        else
            assign heater=1'b0;
    end*/   //上述还没有写完，但是写法以及比较笨了，下述写法简洁干练，对于&和|的使用还需加强
    assign heater = mode & too_cold;
    assign aircon = (~mode) & too_hot;
    assign fan = (mode & too_cold) | ((~mode) & too_hot) | fan_on;
endmodule

3-bit population count

module top_module( 
    input [2:0] in,
    output [1:0] out );
    integer i;
    always@*begin
        out=2'b0;
    for(i=0;i<3;i=i+1)
        begin
            out=out+in[i];
        end
    end
endmodule

为什么这道题用initial去初始化i会出错呢？
Gates and vectors

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
	integer i;
    always @(*) begin
        for(i=0;i<3;i++) begin
            out_both[i] = in[i] & in[i+1];
            out_any[i+1] = in[i+1] | in[i];
            out_different[i] = in[i] ^ in[i+1];
        end
        out_different[3] = in[0] ^ in[3];
    end

endmodule

Even longer vectors

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
	integer i;
    
    always @(*) begin
        for(i=0;i<99;i++) begin
            out_both[i] = in[i] & in[i+1];
            out_any[i+1] = in[i+1] | in[i];
            out_different[i] = in[i] ^ in[i+1];
        end
        out_different[99] = in[0] ^ in[99];
    end

endmodule

---

完成了Basic Gates部分，也是基础部分，所以并没有什么需要特别注明的。