hdlbits-Exams/ece241 2013 q8

考试/ece241 2013 Q8 - HDLBits (01xz.net)

这就是一个序列检测器，并且是一个连续的检测器

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 

    parameter S0 = 2'd0,S1 = 2'd1,S2 = 2'd2;
    reg [1:0] current_state,next_state;

    always @(*) begin
        case(current_state)
            S0: next_state = x ? S1 : S0;
            S1: next_state = x ? S1 : S2;
            S2: next_state = x ? S1 : S0;
        endcase
    end

    always @(posedge clk or negedge aresetn) begin
        if(~aresetn)begin
            current_state <= S0;
        end
        else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        z = (current_state == S2) ? x : 1'b0;
    end

endmodule