hdlbits-Fsm hdlc

Fsm hdlc - HDLBits (01xz.net)

对于状态机，真的是不理解，需要从相关书籍再重头学起，而且看csdn中有提到官方答案，也要去查查

(30条消息) HDLBits答案(19)_Verilog有限状态机(6)_能导致@(posedge)_日拱一卒_未来可期的博客-CSDN博客

  1 //----------------way1----------------------
  2 module top_module(
  3     input clk,
  4     input reset,    // Synchronous reset
  5     input in,
  6     output disc,
  7     output flag,
  8     output err);
  9 
 10     parameter NONE = 4'd0,ONE = 4'd1,TWO = 4'd2;
 11     parameter THREE = 4'd3,FOUR = 4'd4,FIVE = 4'd5;
 12     parameter SIX = 4'd6,ERROR = 4'd7;
 13     parameter DISC = 4'd8,FLAG = 4'd9;
 14 
 15     reg [3:0] current_state,next_state;
 16 
 17     always @(*) begin
 18         case(current_state)
 19             NONE:begin
 20                 next_state = in ? ONE : NONE;
 21             end
 22             ONE:begin
 23                 next_state = in ? TWO : NONE;
 24             end
 25             TWO:begin
 26                 next_state = in ? THREE : NONE;
 27             end
 28             THREE:begin
 29                 next_state = in ? FOUR : NONE;
 30             end
 31             FOUR:begin
 32                 next_state = in ? FIVE : NONE;
 33             end
 34             FIVE:begin
 35                 next_state = in ? SIX : DISC;
 36             end
 37             SIX:begin
 38                 next_state = in ? ERROR : FLAG;
 39             end
 40             DISC:begin
 41                 next_state = in ? ONE : NONE;
 42             end
 43             FLAG:begin
 44                 next_state = in ? ONE : NONE;
 45             end
 46             ERROR:begin
 47                 next_state = in ? ERROR : NONE;
 48             end
 49         endcase
 50     end
 51 
 52     always @(posedge clk) begin
 53         if(reset)begin
 54             current_state <= NONE;
 55         end
 56         else begin
 57             current_state <= next_state;
 58         end
 59     end
 60 
 61     always @(posedge clk) begin
 62         if(reset)begin
 63             disc <= 1'd0;
 64             flag <= 1'd0;
 65             err  <= 1'd0;
 66         end
 67         else begin
 68             case(next_state)
 69                 DISC:begin
 70                     disc <= 1'd1;
 71                     flag <= 1'd0;
 72                     err  <= 1'd0;
 73                 end
 74                 FLAG:begin
 75                     disc <= 1'd0;
 76                     flag <= 1'd1;
 77                     err  <= 1'd0;
 78                 end
 79                 ERROR:begin
 80                     disc <= 1'd0;
 81                     flag <= 1'd0;
 82                     err  <= 1'd1;
 83                 end
 84                 default:begin
 85                     disc <= 1'd0;
 86                     flag <= 1'd0;
 87                     err  <= 1'd0;
 88                 end
 89             endcase
 90         end
 91     end
 92 
 93 endmodule
 94 //----------------way2----------------------
 95 module top_module(
 96     input clk,
 97     input reset,    // Synchronous reset
 98     input in,
 99     output disc,
100     output flag,
101     output err);
102 
103     parameter NONE = 3'd0,DATA = 3'd1;
104     parameter DISC = 3'd2,FLAG = 3'd3,ERROR = 3'd4;
105 
106     reg [2:0] current_state,next_state;
107     reg [2:0] counter;
108 
109     always @(*) begin
110         case(current_state)
111             NONE:begin
112                 next_state = in ? DATA : NONE;
113             end
114             DATA:begin
115                 case(counter)
116                     3'd5:   next_state = in ? DATA : DISC;
117                     3'd6:   next_state = in ? ERROR : FLAG;
118                     default:next_state = in ? DATA : NONE;
119                 endcase
120             end
121             DISC:begin
122                 next_state = in ? DATA : NONE;
123             end
124             FLAG:begin
125                 next_state = in ? DATA : NONE;
126             end
127             ERROR:begin
128                 next_state = in ? ERROR : NONE;
129             end
130         endcase
131     end
132 
133     always @(posedge clk) begin
134         if(reset)begin
135             current_state <= NONE;
136         end
137         else begin
138             current_state <= next_state;
139         end
140     end
141 
142     always @(posedge clk) begin
143         if(reset)begin
144             disc <= 1'd0;
145             flag <= 1'd0;
146             err  <= 1'd0;
147             counter <= 3'd0;
148         end
149         else begin
150             case(next_state)
151                 DATA:begin
152                     disc <= 1'd0;
153                     flag <= 1'd0;
154                     err  <= 1'd0;
155                     counter <= counter + 1'd1;
156                 end
157                 DISC:begin
158                     disc <= 1'd1;
159                     flag <= 1'd0;
160                     err  <= 1'd0;
161                     counter <= 3'd0;
162                 end
163                 FLAG:begin
164                     disc <= 1'd0;
165                     flag <= 1'd1;
166                     err  <= 1'd0;
167                     counter <= 3'd0;
168                 end
169                 ERROR:begin
170                     disc <= 1'd0;
171                     flag <= 1'd0;
172                     err  <= 1'd1;
173                     counter <= 3'd0;
174                 end
175                 default:begin
176                     disc <= 1'd0;
177                     flag <= 1'd0;
178                     err  <= 1'd0;
179                     counter <= 3'd0;
180                 end
181             endcase
182         end
183     end
184 
185 endmodule

 

posted @ 2023-05-06 23:02  江左子固  阅读(45)  评论(0)  编辑  收藏  举报