Vector bit-select and part-select addressing verilog片选写法
摘要:
大端 m m[ a +: b ] == m[ (a+b-1) : a ] m[ a -: b ] == m[ a : (a-b+1) ] 小端 n n[ a +: b ] == n[ a : (a+b-1) ] n[ a -: b ] == n[ (a-b+1) : a ] 阅读全文
posted @ 2018-05-07 09:17 IC新手 阅读(1369) 评论(0) 推荐(0) 编辑