Vector bit-select and part-select addressing verilog片选写法

大端 m

m[ a +: b ] == m[ (a+b-1) : a ]

m[ a -: b ] == m[ a : (a-b+1) ]

小端 n

n[ a +: b ] == n[ a : (a+b-1) ]

n[ a -: b ] == n[  (a-b+1) : a ]

 

module top;
`timescale 10ns/1ns

reg [31:0] big_vect = 'h12345678;
reg [0:31] little_vect = 'h87654321;
reg [63:0] dword;

integer sel;
initial 
begin
 #100
 
 $display("1. big_vect = 0x%h, big_vect[0 +:8] is %h, and big_vect[7 -:8] is %h ", big_vect, big_vect[0 +:8], big_vect[7 -:8] );
 
if (   big_vect[0  +:8] ==    big_vect[7  : 0])begin  $display("   big_vect[0  +:8] ==    big_vect[7  : 0]"); end 
if (little_vect[0  +:8] == little_vect[0  : 7])begin  $display("little_vect[0  +:8] == little_vect[0  : 7]"); end
if (   big_vect[15 -:8] ==    big_vect[15 : 8])begin  $display("   big_vect[15 -:8] ==    big_vect[15 : 8]"); end
if (little_vect[15 -:8] == little_vect[8  :15])begin  $display("little_vect[15 -:8] == little_vect[8  :15]"); end
if (sel >0 && sel < 8) dword[8*sel +:8] = big_vect[7:0]; // Replace the byte selected.

// 注意： big_vect[0:7] 引用错误，同理little_vect[15:8] 也是引用错误。
// if (   big_vect[0  +:8] ==    big_vect[0  : 7])begin  end  

end

endmodule

输出
# 1. big_vect = 0x12345678, big_vect[0 +:8] is 78, and big_vect[7 -:8] is 78 
#    big_vect[0  +:8] ==    big_vect[7  : 0]
# little_vect[0  +:8] == little_vect[0  : 7]
#    big_vect[15 -:8] ==    big_vect[15 : 8]
# little_vect[15 -:8] == little_vect[8  :15]