写简单的tb(testbench)文件来测试之前的FSM控制的LED
先上我之前写的状态机控制的led代码led_test.v
module led_test(clk,led_out); input clk; output reg[3:0] led_out; initial begin led_out=4'b0000; end reg[3:0] state=4'b0000; reg[31:0] timer=32'd0; parameter state_0=4'b0000; parameter state_1=4'b0001; parameter state_2=4'b0010; parameter state_3=4'b0100; parameter state_4=4'b1000; always@(posedge clk) begin case(state) state_0: if(timer>=32'd9999_9999) begin state<=state_1; led_out<=state_1; timer<=32'd0; end else begin state<=state; led_out<=led_out; timer=timer+32'd1; end state_1: if(timer>=32'd9999_9999) begin state<=state_2; led_out<=state_2; timer<=32'd0; end else begin state<=state; led_out<=led_out; timer=timer+32'd1; end state_2: if(timer>=32'd9999_9999) begin state<=state_3; led_out<=state_3; timer<=32'd0; end else begin state<=state; led_out<=led_out; timer=timer+32'd1; end state_3: if(timer>=32'd9999_9999) begin state<=state_4; led_out<=state_4; timer<=32'd0; end else begin state<=state; led_out<=led_out; timer=timer+32'd1; end state_3: if(timer>=32'd9999_9999) begin state<=state_4; led_out<=state_4; timer<=32'd0; end else begin state<=state; led_out<=led_out; timer=timer+32'd1; end state_4: if(timer>=32'd9999_9999) begin state<=state_0; led_out<=state_0; timer<=32'd0; end else begin state<=state; led_out<=led_out; timer=timer+32'd1; end default: state<=state_0; endcase end endmodule
然后下面是我写的一个简陋的tb文件 led_test_tb.v
`timescale 1ns/1ps module led_test_tb(); reg clk; wire[3:0] led_out; led_test a ( .clk(clk), .led_out(led_out) ); initial begin clk=0; end initial begin clk=0; forever #10 clk=~clk; end endmodule
但是今天折腾了半天仍然没有输出正确的波形图,只有激励波形,改天接着修改。下面是初次调出的波形图:
马上要考信号与系统了,我还得滚去复习,还要复习考研,抽空学这个,虽然累,但是乐啊,剩下的仿真波形错误我下次再来改吧。
少一些功利主义的追求,多一些不为什么的坚持!
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