【HDLbits答案】Circuits-Sequential Logic(其二)

目录Circuits-Sequential Logic下 Shift Registers 与 More Circuits 练习题答案

Shift Registers

Shift4

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
always @(posedge clk or posedge areset )begin 
    if(areset )
        q <= 4'd0;
    else if(load )
        q <= data;
    else if(ena )
        q <= {1'b0,q[3:1]};
end 
endmodule

Rotate100

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 
always @(posedge clk )begin 
    if(load )
        q <= data ;
    else begin 
        case(ena )
            2'b01:q <= {q[0],q[99:1]};
            2'b10:q <= {q[98:0],q[99]};
            default:q <= q;
        endcase 
    end         
end 
endmodule

Shift18

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
always @(posedge clk )begin 
    if (load )
        q <= data ;
    else if(ena )begin 
        case(amount)
            2'b00:q <= {q[62:0],1'b0};
            2'b01:q <= {q[55:0],8'b0};
            2'b10:q <= {q[63],q[63:1]};
            2'b11:q <= {{8{q[63]}},q[63:8]};
        endcase 
    end     
end 
endmodule

Lfsr5

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 
always @(posedge clk )begin 
    if(reset )
        q <= 5'h1;
    else begin 
        q[0] <= q[1];
        q[1] <= q[2];
        q[2] <= q[0]^q[3];
        q[3] <= q[4];
        q[4] <= q[0]^1'b0;
    end         
end 
endmodule

Mt2015 lfsr

module top_module (
    input [2:0] SW,      // R
    input [1:0] KEY,     // L and clk
    output [2:0] LEDR);  // Q
    
reg [2:0]    LEDR_next;   
always@(*)begin
    if(KEY[1])begin
        LEDR_next = SW;
    end
    else begin
        LEDR_next[0] = LEDR[2];
        LEDR_next[1] = LEDR[0];
        LEDR_next[2] = LEDR[2] ^ LEDR[1];
    end
end

always@(posedge KEY[0])begin
    LEDR <= LEDR_next;
end
    
endmodule

Lfsr32

module top_module(
    input clk,
    input reset,    
    output [31:0] q
); 
    
reg [31:0]    q_next;
always@(*)begin
    q_next = {q[0], q[31:1]};
    q_next[21] = q[0] ^ q[22];
    q_next[1] = q[0] ^ q[2];
    q_next[0] = q[0] ^ q[1];
end
always@(posedge clk)begin
    if(reset)begin
        q <= 32'd1;
    end
    else begin
        q <= q_next;
    end
end
 
endmodule

Exams/m2014 q4k

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
reg  [2:0] q;
always @(posedge clk )begin 
    if(!resetn )
        {q,out} <= 4'd0;         
    else 
        {q,out} <= {in,q[2:0]};        
end 
endmodule

Exams/2014 q4b

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); 

MUXDFF MUXDFF_u1(
    .e    (KEY[1]),
    .w    (LEDR[1]),
    .l    (KEY[2]),
    .r    (SW[0]),
    .clk(KEY[0]),
    .q  (LEDR[0])
);
MUXDFF MUXDFF_u2(
    .e    (KEY[1]),
    .w    (LEDR[2]),
    .l    (KEY[2]),
    .r    (SW[1]),
    .clk(KEY[0]),
    .q  (LEDR[1])
);
MUXDFF MUXDFF_u3(
    .e    (KEY[1]),
    .w    (LEDR[3]),
    .l    (KEY[2]),
    .r    (SW[2]),
    .clk(KEY[0]),
    .q  (LEDR[2])
);
MUXDFF MUXDFF_u4(
    .e    (KEY[1]),
    .w    (KEY[3]),
    .l    (KEY[2]),
    .r    (SW[3]),
    .clk(KEY[0]),
    .q  (LEDR[3])
);
endmodule

module MUXDFF (
    input    wire    e    ,
    input    wire    w    ,
    input     wire     l    ,
    input     wire     r    ,
    input     wire     clk    ,
    output     reg     q
);
always @(posedge clk )begin 
    case({e,l})
        2'b00:q <= q;
        2'b01:q <= r;
        2'b10:q <= w;
        2'b11:q <= r;
    endcase 
end 
endmodule

Exams/ece241 2013 q12

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
reg [7:0] q;

assign Z = q[{A, B, C}];
always @(posedge clk )begin 
    if(enable )
        q <= {q[6:0],S };
    else 
        q <= q;
end 
endmodule

More Circuits

Rule90

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
always @(posedge clk )begin 
    if(load )
        q <= data;
    else 
        q <= {q[510:0],1'b0} ^ {1'b0,q[511:1]};
end 
endmodule

Rule110

always@(posedge clk)begin
    if(load)begin
        q <= data;
    end
    else begin
        q <= ~q & {q[510:0], 1'b0} | 
            ~{1'b0, q[511:1]}& {q[510:0], 1'b0} | 
            ~{1'b0, q[511:1]} & q | 
            q & ~{q[510:0], 1'b0};
    end
end

Conwaylife

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output [255:0] q 
); 
    
reg [3:0]    sum;
integer i;

always@(posedge clk)begin
    if(load)begin
        q <= data;
    end
    else begin
        for(i = 0; i <= 255; i = i + 1)begin
            if(i == 0)begin
                sum = q[255] + q[240] + q[241] + q[15] + q[1] + q[31] + q[16] + q[17];
            end
            else if(i == 15)begin
                sum = q[254] + q[255] + q[240] + q[14] + q[0] + q[30] + q[31] + q[16];
            end
            else if(i == 240)begin
                sum = q[239] + q[224] + q[225] + q[255] + q[241] + q[15] + q[0] + q[1];
            end
            else if(i == 255)begin
                sum = q[238] + q[239] + q[224] + q[254] + q[240] + q[14] + q[15] + q[0];
            end
            else if(i > 0 && i < 15)begin
                sum = q[i + 239] + q[i + 240] + q[i + 241] + q[i - 1] + q[i + 1] + q[i + 15] + q[i + 16] + q[i + 17];
            end
            else if(i > 240 && i < 255)begin
                sum = q[i -17] + q[i - 16] + q[i - 15] + q[i - 1] + q[i + 1] + q[i - 241] + q[i - 240] + q[i - 239];
            end
            else if(i % 16 == 0)begin
                sum = q[i -1] + q[i - 16] + q[i - 15] + q[i + 15] + q[i + 1] + q[i + 31] + q[i + 16] + q[i + 17];
            end
            else if(i % 16 == 15)begin
                sum = q[i -17] + q[i - 16] + q[i - 31] + q[i - 1] + q[i - 15] + q[i + 15] + q[i + 16] + q[i + 1];
            end
            else begin
                sum = q[i - 17] + q[i - 16] + q[i - 15] + q[i - 1] + q[i + 1] + q[i + 15] + q[i + 16] + q[i + 17];
            end
            case(sum)
                4'd2:begin
                    q[i] <= q[i];
                end
                4'd3:begin
                    q[i] <= 1'b1;
                end
                default:begin
                    q[i] <= 1'b0;
                end
            endcase
        end
    end
end       
 
endmodule
————————————————
题目给我看懵了,这个没写出来,复制别人的
版权声明:本文为CSDN博主「wangkai_2019」的原创文章,
原文链接:https://blog.csdn.net/wangkai_2019/article/details/106296833

 

posted @ 2021-03-12 21:51  IntoTheSky  阅读(321)  评论(0编辑  收藏  举报