【HDLbits答案】Circuits-Sequential Logic（其一）
目录Circuits-Sequential Logic下 Latches and Flip-Flops 与 Counters 练习题答案
这部分有些难度，头秃。。。
Latches and Flip-Flops
Dff
module top_module ( input clk, input d, output reg q ); always @(posedge clk ) q <= d ; endmodule
Dff8
module top_module ( input clk, input [7:0] d, output [7:0] q ); always @(posedge clk ) q <= d ; endmodule
Dff8r
module top_module ( input clk, input reset, input [7:0] d, output [7:0] q ); always @(posedge clk )begin if(reset) q <= 8'd0; else q <= d ; end endmodule
Dff8p
module top_module ( input clk, input reset, input [7:0] d, output [7:0] q ); always @(negedge clk )begin if(reset) q <= 8'h34; else q <= d ; end endmodule
Dff8ar
module top_module ( input clk, input areset, input [7:0] d, output [7:0] q ); always @(posedge clk or posedge areset )begin if(areset ) q <= 8'd0; else q <= d ; end endmodule
Dff16e
module top_module ( input clk, input resetn, input [1:0] byteena, input [15:0] d, output [15:0] q ); always @(posedge clk )begin if(!resetn) q <= 16'd0; else begin if(byteena[0]) q[7:0] <= d[7:0] ; else q[7:0] <= q[7:0] ; if(byteena[1]) q[15:8] <= d[15:8] ; else q[15:8] <= q[15:8] ; end end endmodule
Exams/m2014 q4a
module top_module ( input d, input ena, output q); always@(*)begin if(ena == 1'b1) q = d; end endmodule
Exams/m2014 q4b
module top_module ( input clk, input d, input ar, output q); always @(posedge clk or posedge ar )begin if(ar ) q <= 1'b0 ; else q <= d; end endmodule
Exams/m2014 q4c
module top_module ( input clk, input d, input r, output q); always @(posedge clk )begin if(r ) q <= 1'b0 ; else q <= d; end endmodule
Exams/m2014 q4d
module top_module ( input clk, input in, output reg out); always@(posedge clk)begin out <= in ^ out; end endmodule
Mt2015 muxdff
module top_module ( input clk, input L, input r_in, input q_in, output reg Q); always@(posedge clk)begin if(L) Q <= r_in; else Q <= q_in; end endmodule
Exams/2014 q4a
module top_module ( input clk, input w, R, E, L, output Q ); reg mid,D; always @(* )begin if(E) mid <= w; else mid <= Q; if(L) D <= R; else D <= mid; end always@(posedge clk)begin Q <= D; end endmodule
Exams/ece241 2014 q4
module top_module ( input clk, input x, output z ); reg [2:0] Q; always @(posedge clk )begin Q[0] <= Q[0]^x; Q[1] <= (~Q[1])&x; Q[2] <= (~Q[2])|x; end assign z = ~(|Q); endmodule
Exams/ece241 2013 q7
module top_module ( input clk, input j, input k, output Q); always @(posedge clk )begin case({j,k }) 2'b00:Q <= Q; 2'b01:Q <= 1'b0; 2'b10:Q <= 1'b1; 2'b11:Q <= ~Q; endcase end endmodule
Edgedetect
module top_module ( input clk, input [7:0] in, output [7:0] pedge ); reg [7:0] in_dly; always @(posedge clk )begin in_dly <= in; pedge <= in & ~in_dly; end endmodule
Edgedetect2
module top_module ( input clk, input [7:0] in, output [7:0] anyedge ); reg [7:0] in_dly; always @(posedge clk )begin in_dly <= in; anyedge <= in ^ in_dly; end endmodule
Edgecapture
module top_module ( input clk, input reset, input [31:0] in, output [31:0] out ); reg [31:0] in_dly; always @(posedge clk )begin in_dly <= in; end always @(posedge clk )begin if(reset ) out <= 32'd0; else out <= ~in & in_dly | out ; end endmodule
Dualedge
module top_module ( input clk, input d, output q ); reg q_d1,q_d2; assign q = q_d1 ^ q_d2; always@(posedge clk)begin q_d1 <= d ^ q_d2; end always@(negedge clk)begin q_d2 <= d ^ q_d1; end endmodule
Counters
Count15
module top_module ( input clk, input reset, output [3:0] q); always @(posedge clk )begin if (reset) q <= 4'd0; else q <= q + 1'b1; end endmodule
Count10
module top_module ( input clk, input reset, output [3:0] q); always @(posedge clk )begin if (reset) q <= 4'd0; else if (q == 4'h9 ) q <= 4'd0; else q <= q + 1'b1; end endmodule
Count1to10
module top_module ( input clk, input reset, output [3:0] q); always @(posedge clk )begin if (reset) q <= 4'd1; else if (q == 4'ha ) q <= 4'd1; else q <= q + 1'b1; end endmodule
Countslow
module top_module ( input clk, input slowena, input reset, output [3:0] q); always @(posedge clk )begin if(reset) q <= 4'd0; else if(slowena)begin if(q == 4'h9 ) q <= 4'd0; else q <= q + 1'b1; end else q <= q; end endmodule
Exams/ece241 2014 q7a
module top_module ( input clk, input reset, input enable, output [3:0] Q, output c_enable, output c_load, output [3:0] c_d ); assign c_enable = enable; assign c_load = reset | ((Q == 4'd12) && enable == 1'b1); assign c_d = c_load ? 4'd1 : 4'd0; count4 count4_inst(clk, c_enable, c_load, c_d, Q); endmodule
Exams/ece241 2014 q7b
module top_module ( input clk, input reset, output OneHertz, output [2:0] c_enable ); wire [3:0] q1,q2,q3; assign c_enable = {q1==4'd9 && q2==4'd9,q1 == 4'd9,1'b1}; assign OneHertz = q1==4'd9 && q2==4'd9 && q==4'd9; bcdcount counter0 (clk, reset, c_enable[0],q1); bcdcount counter1 (clk, reset, c_enable[1],q2); bcdcount counter2 (clk, reset, c_enable[2],q3); endmodule
Countbcd
module top_module ( input clk, input reset, output [3:1] ena, output [15:0] q); assign ena = {q[11:8]==4'd9 && q[7:4]==4'd9 && q[3:0]==4'd9, q[7:4]==4'd9 && q[3:0]==4'd9,q[3:0]==4'd9}; counter10 counter10_inst1( .clk (clk), .slowena(1'b1), .reset (reset), .q (q[3:0]) ); counter10 counter10_inst2( .clk (clk), .slowena(ena[1]), .reset (reset), .q (q[7:4]) ); counter10 counter10_inst3( .clk (clk), .slowena(ena[2]), .reset (reset), .q (q[11:8]) ); counter10 counter10_inst4( .clk (clk), .slowena(ena[3]), .reset (reset), .q (q[15:12]) ); endmodule module counter10 ( input clk, input slowena, input reset, output [3:0] q); always @(posedge clk )begin if(reset) q <= 4'd0; else if(slowena)begin if(q == 4'h9 ) q <= 4'd0; else q <= q + 1'b1; end else q <= q; end endmodule
Count clock
module top_module( input clk, input reset, input ena, output pm, output [7:0] hh, output [7:0] mm, output [7:0] ss); wire ena_s1,ena_s2, ena_min1,ena_min2, ena_hour1,ena_hour2; reg pm1; assign ena_s1 = ena & (~reset); assign ena_s2 = ena & (ss[3:0]==4'h9); assign ena_min1 = (ss[7:0]==8'h59); assign ena_min2 = (mm[3:0]==4'h9)&(ss[7:0]==8'h59); assign ena_hour1 = (ss==8'h59)&(mm==8'h59); assign ena_hour2 = (ss==8'h59)&(mm==8'h59)&((hh==8'h09)|(hh==8'h12)); always @(posedge clk )begin if(reset ) ss[3:0] <= 4'd0; else if(ena_s1)begin if(ss[3:0]==4'h9) ss[3:0] <= 4'd0; else ss[3:0] <= ss[3:0] + 1'b1; end else ss[3:0] <= ss[3:0]; end always @(posedge clk )begin if(reset ) ss[7:4] <= 4'd0; else if(ena_s2 )begin if(ss[7:4]==4'h5) ss[7:4] <= 4'd0; else ss[7:4] <= ss[7:4] + 1'b1; end else ss[7:4] <= ss[7:4]; end always @(posedge clk )begin if(reset ) mm[3:0] <= 4'd0; else if(ena_min1)begin if(mm[3:0]==4'h9) mm[3:0] <= 4'd0; else mm[3:0] <= mm[3:0] + 1'b1; end else mm[3:0] <= mm[3:0]; end always @(posedge clk )begin if(reset ) mm[7:4] <= 4'd0; else if(ena_min2)begin if(mm[7:4]==4'h5) mm[7:4] <= 4'd0; else mm[7:4] <= mm[7:4] + 1'b1; end else mm[7:4] <= mm[7:4]; end always @(posedge clk )begin if(reset ) hh[3:0] <= 4'd2; else if(ena_hour1)begin if(hh==8'h12 ) hh[3:0] <= 4'd1; else if(hh[3:0] == 4'd9) hh[3:0] <= 4'd0; else hh[3:0] <= hh[3:0] + 4'd1; end else hh[3:0] <= hh[3:0]; end always @(posedge clk )begin if(reset ) hh[7:4] <= 4'd1; else if(ena_hour2)begin if(hh[7:4]==4'h1) hh[7:4] <= 4'd0; else hh[7:4] <= hh[7:4] + 1'b1; end else hh[7:4] <= hh[7:4]; end always @(posedge clk )begin if(reset ) pm1 <= 0; else if((ena_hour1)&&(hh==8'h11)) pm1 <= ~pm1; end assign pm = pm1; endmodule
