【HDLbits答案】Circuits-Combinational Logic（其二）

目录Circuits-Combinational Logic下Arithmetic circuits 与 Karnaugh Map to Circuit练习题答案

Arithmetic circuits

Hadd

module top_module( 
    input a, b,
    output cout, sum );
assign sum = a^b;
assign cout = a&b;
endmodule

Fadd

module top_module( 
    input a, b, cin,
    output cout, sum );
assign sum = a^b^cin;
assign cout = (a&b)|(a&cin)|(b&cin);
endmodule

Adder3

module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
wire cout1,cout2,cout3,sum1,sum2,sum3;
fadd fadd_u1(a[0],b[0],cin  ,cout1,sum1);
fadd fadd_u2(a[1],b[1],cout1,cout2,sum2);
fadd fadd_u3(a[2],b[2],cout2,cout3,sum3);
assign cout = {cout3,cout2,cout1};
assign sum  = {sum3,sum2,sum1};
endmodule
module fadd ( 
    input a, b, cin,
    output cout, sum );
assign sum = a^b^cin;
assign cout = (a&b)|(a&cin)|(b&cin);
endmodule

Exams/m2014 q4j

module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);
wire[3:0]    sum_1;
wire[3:0]    cout;
    
assign sum_1[0] = x[0] ^ y[0];
assign sum_1[1] = x[1] ^ y[1] ^ cout[0];
assign sum_1[2] = x[2] ^ y[2] ^ cout[1];
assign sum_1[3] = x[3] ^ y[3] ^ cout[2];
assign cout[0] = x[0] & y[0];
assign cout[1] = x[1] & y[1] | x[1] & cout[0] | y[1] & cout[0];
assign cout[2] = x[2] & y[2] | x[2] & cout[1] | y[2] & cout[1];
assign cout[3] = x[3] & y[3] | x[3] & cout[2] | y[3] & cout[2];
    
assign sum = {cout[3], sum_1};
endmodule

Exams/ece241 2014 q1c

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
); 
 
     assign s = a + b; 
     assign overflow = a[7] & b[7] & ~s[7]  |  ~a[7] & ~b[7] & s[7];

endmodule

Adder100

module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
assign {cout,sum} = a + b + cin ;
endmodule

Bcdadd4

module top_module( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
wire cout1,cout2,cout3;    
bcd_fadd bcd_fadd_inst1(
    .a        (a[3:0]),
    .b        (b[3:0]),
    .cin    (cin),
    .cout    (cout1),
    .sum    (sum[3:0])
);
bcd_fadd bcd_fadd_inst2(
    .a        (a[7:4]),
    .b        (b[7:4]),
    .cin    (cout1),
    .cout    (cout2),
    .sum    (sum[7:4])
);
bcd_fadd bcd_fadd_inst3(
    .a        (a[11:8]),
    .b        (b[11:8]),
    .cin    (cout2),
    .cout    (cout3),
    .sum    (sum[11:8])
);
bcd_fadd bcd_fadd_inst4(
    .a        (a[15:12]),
    .b        (b[15:12]),
    .cin    (cout3),
    .cout    (cout),
    .sum    (sum[15:12])
);
    
endmodule

Karnaugh Map to Circuit

Kmap1

module top_module(
    input a,
    input b,
    input c,
    output out  ); 
assign out = a|b|c;
endmodule

Kmap2

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
assign out = ~a & ~d | ~b & ~c | b & c & d | a & c & d;
endmodule

Kmap3

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  );   
assign out = ~b & c | a & c | a & ~d;
endmodule

Kmap4

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
//out = a'bc'd'+ab'c'd' + a'b'c'd+abc'd + a'bcd+ab'cd + a'b'cd'+abcd'
assign out =~a&b&~c&~d | a&~b&~c&~d| 
            ~a&~b&~c&d | a&b&~c&d  | 
            ~a&b&c&d   | a&~b&c&d  | 
            ~a&~b&c&~d | a&b&c&~d;
endmodule

Exams/ece241 2013 q2

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
); 
assign out_sop = c & d|~a & ~b & c;
assign out_pos = ~((~c|~d) & (a|b|~c));
endmodule

Exams/m2014 q3

module top_module (
    input [4:1] x, 
    output f );
    assign f = ~x[1]&x[3] | x[4]&x[2];
endmodule

Exams/2012 q1g

module top_module (
    input [4:1] x,
    output f
); 
assign f = ~x[1] & x[3] | x[2] & x[3] & x[4] | ~x[2] & ~x[4];
endmodule

Exams/ece241 2014 q3

module top_module (
    input c,
    input d,
    output [3:0] mux_in
);
    assign mux_in[0] = c ? 1'b1 : d;
    assign mux_in[1] = 1'b0;
    assign mux_in[2] = d ? 1'b0 : 1'b1;
    assign mux_in[3] = c ? d : 1'b0;     
endmodule