【HDLbits答案】Verilog Language-More Verilog Features

目录Verilog Language-More Verilog Features下练习题答案

Conditional

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);
wire [7:0] mid1,mid2;

assign mid1 = (a<=b)?a:b;
assign mid2 = (c<=d)?c:d;
assign min  = (mid1<=mid2)?mid1:mid2;    

endmodule

Reduction

module top_module (
    input [7:0] in,
    output parity); 
assign parity = ^in[7:0];
endmodule

Gates100

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
assign out_and     = &in[99:0];
assign out_or     = |in[99:0];
assign out_xor    = ^in[99:0];

endmodule

Vector100r

module top_module( 
    input [99:0] in,
    output [99:0] out
);
always @(*)begin 
    for(int i=0;i<100;i=i+1)
        begin
            out[i] = in[99-i];
        end 
end 
endmodule

Popcount255

module top_module( 
    input [254:0] in,
    output [7:0] out );
always @(*)begin 
    out = 8'd0;
    for(int i=0;i<255;i=i+1)begin 
        if(in[i]==1'b1)
            out = out + 1'b1;
        else 
            out = out;
    end     
end 
endmodule

Adder100i

module top_module(
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
 
    genvar i;
    generate for(i=0;i<=99;i++)
    begin:adder
        if(i==0)begin
            assign{cout[0],sum[0]}=a[0]+b[0]+cin;
        end
        else begin
            assign{cout[i],sum[i]}=a[i]+b[i]+cout[i-1];
        end
    end
    endgenerate      
endmodule

Bcdadd100

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
wire [99:0] couti;
assign cout = couti[99];
genvar i;
generate for(i=0;i<100;i=i+1)
    begin:adder 
        if(i==0)begin 
            bcd_fadd bcd_fadd_inst1(
                .a         (a[3:0]),
                .b         (b[3:0]),
                .cin     (cin),
                .cout     (couti[0]),
                .sum     (sum[3:0])
            );
            end 
        else begin 
            bcd_fadd bcd_fadd_insti(
                .a         (a[4*i+3:4*i]),
                .b         (b[4*i+3:4*i]),
                .cin     (couti[i-1]),
                .cout     (couti[i]),
                .sum     (sum[4*i+3:4*i])
            );
            end     
    end 
endgenerate 

endmodule