【HDLbits答案】Verilog Language-Prucedures

目录Verilog Language-Prucedures下练习题答案

Alwaysblock1

module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
assign out_assign = a&b;
always @(*)begin 
    out_alwaysblock <= a&b;
end 

endmodule

Alwaysblock2

module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
assign out_assign = a^b;
always @(*)begin 
out_always_comb = a^b;
end 

always @(posedge clk )
    out_always_ff <= a^b;

endmodule

Always if

module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
assign out_assign = ((sel_b1==1'b1)&&(sel_b2==1'b1))?b:a;
always @(*)begin
    if((sel_b1==1'b1)&&(sel_b2==1'b1))
        out_always <= b;
    else
        out_always <= a;
end 
endmodule

Always if2

module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); 

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else
           shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived)
           keep_driving = ~gas_tank_empty;
        else
           keep_driving = 0;
    end

endmodule

Always case

module top_module ( 
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   );

    always@(*) begin  
        case(sel )
            3'd0:out = data0;
            3'd1:out = data1;
            3'd2:out = data2;
            3'd3:out = data3;
            3'd4:out = data4;
            3'd5:out = data5;
            default:out = 3'd0;
        endcase 
    end 

endmodule

Always case2

module top_module (
    input [3:0] in,
    output reg [1:0] pos  );
always@(*)begin 
    if(in[0])
        pos = 2'b00;
    else    begin 
        case(in )
        4'b0010,4'b0110,4'b1110,4'b1010:    pos = 2'b01;
        4'b0100,4'b1100:    pos = 2'b10;
        4'b1000:            pos = 2'b11;
        default:pos = 2'b0;
        endcase
      end 
end 

endmodule

Always casez

module top_module (
    input [7:0] in,
    output reg [2:0] pos  );
always @(*)begin
    casez(in )
        8'bzzzzzzz1:pos = 3'd0;
        8'bzzzzzz1z:pos = 3'd1;
        8'bzzzzz1zz:pos = 3'd2;
        8'bzzzz1zzz:pos = 3'd3;
        8'bzzz1zzzz:pos = 3'd4;
        8'bzz1zzzzz:pos = 3'd5;
        8'bz1zzzzzz:pos = 3'd6;
        8'b1zzzzzzz:pos = 3'd7;
        default:   pos = 3'd0;
    endcase 
end 

endmodule

Always nolatches

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    
always @(*)begin 
    left = 1'b0;down = 1'b0;right = 1'b0;up = 1'b0;
    case(scancode )
        16'he06b:left    = 1'b1;
        16'he072:down    = 1'b1;
        16'he074:right    = 1'b1;
        16'he075:up        = 1'b1;
    endcase 
end 

endmodule