HDLbits（1）

3、wire

assign out = in ;

4、wire4

assign {w,x,y,z} = {a,b,b,c} ;

5、notgate

assign out = ~ in ;

6、andgate

assign out = a & b ;

7、norgate

assign out = ~(a|b) ;

8、xorgate

xor为异或。xnor为异或非

assign out =  !(a^b) ;

9、wire_decl

wire wire1,wire2,wire3;
assign wire1 = a & b ;
assign wire2 = c & d ;
assign wire3 = wire1 | wire2 ;
assign out = wire3 ;
assign out_n = !wire3 ;

10、7458

assign p2y = (p2c & p2d) | (p2a & p2b) ;
assign p1y = (p1a & p1c & p1b) | (p1f & p1d & p1e) ;

11、Vector0

assign outv = vec ;
assign {o2,o1,o0} = vec;

12、Vector1

assign {out_hi,out_lo} = in ;

13、Vector2

assign  out = {in[7:0],in[15:8],in[23:16],in[31:24]} ;

14、Vectorgates

 assign out_or_bitwise = a | b;
 assign out_or_logical = a || b ;
 assign out_not = {~b,~a} ;

15、gate4

assign {out_and,out_or,out_xor} = {&in,|in,^in} ;

16、Vector3

assign {w,x,y,z} = {a,b,c,d,e,f,2'b11} ;

17、Vectorr

 generate
     genvar i;
     for(i= 0 ; i <8 ; i = i + 1)
         begin :my_block
         	assign out[i] = in[8-i-1];
         end
 endgenerate 

错误写法：assign out[7:0] = in[0:7]编译不通过

另外，使用generate块必须起名字，否则编译不通过

18、Vector4

assign out = {{24{in[7]}},in} ;

注意24{in[7]}也要被{}包起来

19、Vector5

wire [24:0]aaaaa;
wire [24:0]abcde; 
assign aaaaa = {{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}};
assign abcde = {5{a,b,c,d,e}};
assign out = ~(aaaaa ^ abcde);

20、module

    mod_a inst(
        .out(out),
        .in1(a),
        .in2(b)
    );

21、module pos

    mod_a inst(
      out1,out2,a,b,c,d
    );

22、module name

    mod_a inst(
        .in1(a),
        .in2(b),
        .in3(c),
        .in4(d),
        .out1(out1),
        .out2(out2)
    );
    

23、module_shift

    my_dff inst1(clk,d,q1);
    my_dff inst2(clk,q1,q2);
    my_dff inst3(clk,q2,q);

24、module_shift_8

    wire[7:0] q1,q2,q3;
    my_dff8 inst1(clk,d,q1);
    my_dff8 inst2(clk,q1,q2);
    my_dff8 inst3(clk,q2,q3);
    
    always @(*)
        begin
        	case(sel) 
            	0: q = d ;
            	1: q = q1;
            	2: q = q2;
            	3: q = q3;
            endcase
        end

25、module add

    wire		cout;
    
    add16 add_low(
        .a      (a[15:0]	),
        .b      (b[15:0]	),
        .cin	(1'b0		),
        .sum	(sum[15:0]	),
        .cout	(cout		)
    );
 
    add16 add_high(
        .a      (a[31:16]	),
        .b      (b[31:16]	),
        .cin	(cout		),
        .sum	(sum[31:16]	),
        .cout	(   		)
    );

26、module fadd

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//
    wire cout ;
    add16 add_low(
        .a(a[15:0]),
        .b(b[15:0]),
        .cin(1'b0),
        .cout(cout),
        .sum(sum[15:0])
    );
        add16 add_high(
            .a(a[31:16]),
            .b(b[31:16]),
            .cin(cout),
       		.cout(),
            .sum(sum[31:16])
    );

endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );

// Full adder module here
    assign {cout,sum} = a + b+ cin ;

endmodule

27、module cseladd

    wire sel;
    wire [15:0]sum_high1;
    wire [15:0]sum_high2 ;
    add16 add_low(
        .a(a[15:0]),
        .b(b[15:0]),
        .cin(1'b0),
        .sum(sum[15:0]),
        .cout(sel)
    );
    add16 add_high1(
        .a(a[31:16]),
        .b(b[31:16]),
        .cin(1'b0),
        .sum(sum_high1),
        .cout()
    );
        add16 add_high2(
        .a(a[31:16]),
        .b(b[31:16]),
            .cin(1'b1),
            .sum(sum_high2),
        .cout()
    );
    assign sum[31:16] = sel ? sum_high2 : sum_high1 ;

28、module addsub

    wire [31:0] bin;
    wire cout ;
    
    assign bin = {32{sub}} ^ b;
    
    add16 add_low(
        .a(a[15:0]),
        .b(bin[15:0]),
        .cin(sub),
        .cout(cout),
        .sum(sum[15:0])
    );
        add16 add_high(
            .a(a[31:16]),
            .b(bin[31:16]),
            .cin(cout),
        	.cout(),
            .sum(sum[31:16])
    );

29、always bock1

assign out_assign = a & b ;
always @(*)
    begin
        out_alwaysblock = a& b;
    end

30、alwaysbock2

    assign out_assign = a ^ b;
    always @(*)
        begin
            out_always_comb = a ^ b;
        end
    always @(posedge clk)
        begin
            out_always_ff <= a ^ b;
        end
    

31、always if

    always @(*)
        begin
            if((sel_b1 == 1) &&(sel_b2 == 1) )
                out_always <= b;
            else
                out_always <= a;
        end
    assign out_assign = ((sel_b1 ==1) & (sel_b2 == 1)) ? b : a; 

32、always if2

在组合逻辑中，if分支一定要写全，否则输出只在指定的条件变化，在未指定的条件保持不变。但是组合逻辑无法记忆状态，这就会导致综合时输出端连接在输入端作为输入产生锁存器。

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else
            shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived)
           keep_driving = ~gas_tank_empty;
        else
            keep_driving = ~arrived ;
    end

33、always case

   always@(*) begin  // This is a combinational circuit
        case(sel)
            0 :out <= data0 ;
            1 :out <= data1 ;
            2 :out <= data2 ;
            3 :out <= data3 ;
            4 :out <= data4 ;
            5 :out <= data5 ;
            default:out <= 4'b0;
        endcase
    end

34、always case2

    always@(*)begin
        casez(in)
            4'bzzz1:pos = 2'd0;
            4'bzz10:pos = 2'd1;
            4'bz100:pos = 2'd2;
            4'b1000:pos = 2'd3;
            default:pos = 2'd0;
        endcase
    end

注意是casez不是case

35、always casez

always @(*)
    casez (in)
        8'bzzzz_zzz1: pos = 0;
        8'bzzzz_zz1z: pos = 1;
        8'bzzzz_z1zz: pos = 2;
        8'bzzzz_1zzz: pos = 3;
        8'bzzz1_zzzz: pos = 4;
        8'bzz1z_zzzz: pos = 5;
        8'bz1zz_zzzz: pos = 6;
        8'b1zzz_zzzz: pos = 7;
        default: pos = 0;
    endcase

36、always nolatches

    always @(*)
        begin
            case(scancode)
                16'he06b:
                    begin
                    	up = 1'b0; down = 1'b0; left = 1'b1; right = 1'b0;
                	end
                16'he072:
                    begin
                    	up = 1'b0; down = 1'b1; left = 1'b0; right = 1'b0;
                	end
                16'he074:
                    begin
                    	up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b1;
                	end
                16'he075:
                    begin
                    	up = 1'b1; down = 1'b0; left = 1'b0; right = 1'b0;
                	end
                default :
                    begin
                        up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
                    end
            endcase
        end

37、Conditional

    wire [7:0]	min_ab,min_cd;
    assign min_ab = a>b ? b : a;
    assign min_cd = c>d ? d : c ;
    assign min = min_ab > min_cd ? min_cd : min_ab ; 

38、Reduction

 assign parity = ^in;

奇偶校验，就是通过添加一位，使源数据中1的个数变为奇数或者偶数。

39、gates 100

    assign out_and = &in  ;
    assign out_or = |in ;
    assign out_xor = ^in;

40、vector100r

    generate
        genvar i;
        for(i=0;i<100;i = i+1)
            begin:myblock
            	assign out[i] = in[100-i-1];
            end
    endgenerate

注意给generate块起名字。

41、Popcount255

    integer i;
    always @(*)
        begin
            out = 8'b0000_0000 ;
            for(i=0;i<=254;i++)
                begin
                    if(in[i]==1'b1)
                        out = out +1;
                    else
                        out = out +0;
                end   
        end 

注意out要先给一个初值，实际问题中可用rst控制。

42、adder 100i

    generate
        genvar i;
        for(i=0;i<100;i=i+1)
            begin:adder
                if(i==0)
                    assign {cout[0],sum[0]} = a[0]+b[0]+cin;
                else
                    assign {cout[i],sum[i]} = a[i]+b[i]+cout[i-1];
            end
    endgenerate

43、bcdadd100

    wire [99:0] cout_in;
    
    generate
        genvar i;
        for(i=0;i<100;i=i+1)
            begin:bcdadd
                if(i==0)
                    bcd_fadd bcd_fadd_0(
                        .a(a[3:0]),
                        .b(b[3:0]),
                        .cin(cin),
                        .cout(cout_in[0]),
                        .sum(sum[3:0])
                    );
                else
                    bcd_fadd bcd_fadd_i(
                        .a(a[4*i+3:4*i]),
                        .b(b[4*i+3:4*i]),
                        .cin(cout_in[i-1]),
                        .cout(cout_in[i]),
                        .sum(sum[4*i+3:4*i])
                    );
            end
    endgenerate
    assign cout = cout_in[99] ;

44、Exams/m2014 q4h

assign out = in ;