Verilog碎碎念

  • We normally have to reset flip-flops, thus every time the clock makes the transition from 0 to 1 (posedge), we check if reset is asserted (synchronous reset), then we go on with normal logic. If we look closely we see that in the case of combinational logic we had "=" for assignment, and for the sequential block we had the "<=" operator. Well, "=" is blocking assignment and "<=" is nonblocking assignment. "=" executes code sequentially inside a begin / end, whereas nonblocking "<=" executes in parallel.
  • 异步清零可以不顾时钟信号,只要清零信号到来就进行清零操作。同步清零即使清零信号有效也要等时钟信号有效沿到来时才清零
  • set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SW_IBUF[0]}]
  • 不能有两个always语句同时对某一reg或wire执行赋值,因为会导致数据冒险。
  • always语句只能对边沿触发敏感或者对电平触发敏感,无法同时对两者敏感。
posted @ 2017-11-20 09:23  ichneumon  阅读(196)  评论(0编辑  收藏  举报