VCS expand macro

为了在调试中理解宏是如何展开的，可以在vcs编译时加上-Xman=4（或其他）的选项

VCS手册中描述如下：

-Xmangle=number
Produces a mangled version of in put, changing variable names
to words from list. Useful to get an entire Verilog design into a
single file. Output is saved in the  tokens.v  file. You can
substitute  -Xman for  -Xmangle .
The argument number  can be 1, 4, 12, or 28:
-Xman=1
Randomly changes names and  identifiers, and removes
comments, to provide more secure code.

-Xman=4
Preserves variable names, but removes comments.
-Xman=12
Does the same thing as -Xman=4 , but also enters, in comments,
the original source file name  and the line number of each
module header.
-Xman=28
Does the same thing as -Xman=12, but also writes at the bottom
of the file comprehensive statistics about the contents of the
original source file.

举例如下：

`timescale 1ns/1ps
`define sum(a,b) a+b
program test();
    `timescale 10ps/10ps
    initial begin
        $display("sum",`sum(4,5));
    end
endprogram

 输入：

vcs -sverilog -Xman=4 test.sv -R

输出的tokens.v中：

`noprtcoerce
`noinline
`timescale 10ps/10ps

`portcoerce
`noinline 
`timescale 1ns/1ps
program test;

    initial begin
      $display("sum:",(4+5));
    end
endprogram