Edge和Level触发的中断
原文地址：http://www.cnblogs.com/liloke/archive/2011/04/12/2014205.html
异步I/O中的Edge-Triggered和Level-Triggered是非常重要的概念；Edge-Triggered字面上理解就是指“边界触发”，说的是当状态变化的时候触发，以后如果状态一直没有变化或没有重新要求系统给出通知，将不再通知应用程序；Level-Triggered是指“状态触发”，说的是在某种状态下触发，如果一直在这种状态下就一直触发。两种触发方式各有用途，应根据不同的应用采用不同的触发方式。select一般默认采用的是Level-Triggered，而EPoll既可以采用Edge-Triggered，也可以采用Level-Triggered，默认是Level-Triggered，而MS的CPIO按这种定义来说应该属于Edge-Triggered。对于已经封装好的异步I/O架构来说，具体采用哪种方式其实无伤大雅，因为无论采用哪种方式，都需要在内部都实现正确了，并且让使用者不再关心这种具体的触发方式为好
边缘触发是指每当状态变化时发生一个io事件，条件触发是只要满足条件就发生一个io事件。举个读socket的例子，假定经过长时间的沉默后，现在来了100个字节，这时无论边缘触发和条件触发都会产生一个read ready notification通知应用程序可读。应用程序读了50个字节，然后重新调用api等待io事件。这时条件触发的api会因为还有50个字节可读从而立即返回用户一个read ready notification。而边缘触发的api会因为可读这个状态没有发生变化而陷入长期等待。因此在使用边缘触发的api时，要注意每次都要读到socket返回EWOULDBLOCK为止，否则这个socket就算废了。而使用条件触发的api时，如果应用程序不需要写就不要关注socket可写的事件，否则就会无限次的立即返回一个write ready notification。大家常用的select就是属于条件触发这一类，以前本人就犯过长期关注socket写事件从而CPU 100%的毛病。
I didn't read you document really, but I can understand why you are confused. But it is a very simple concept really. Let me explain.
Triggering: This means making a circuit active. Making a circuit active means allowing the circuit to take input and give output. Like for example supposed we have a flip-flop. When the circuit is not triggered, even if you give some input data, it will not change the data stored inside the flip-flop nor will it change the output Q or Q'. Now there are basically two types of triggering. The triggering is given in form of a clock pulse or gating signal. Depending upon the type of triggering mechanism used, the circuit will become active at specific states of the clock pulse.
-
Level Triggering: In level triggering the circuit will become active when the gating or clock pulse is on a particular level. This level is decided by the designer. We can have a negative level triggering in which the circuit is active when the clock signal is low or a positive level triggering in which the circuit is active when the clock signal is high.
-
Edge Triggering: In edge triggering the circuit becomes active at negative or positive edge of the clock signal. For example if the circuit is positive edge triggered, it will take input at exactly the time in which the clock signal goes from low to high. Similarly input is taken at exactly the time in which the clock signal goes from high to low in negative edge triggering. But keep in mind after the the input, it can be processed in all the time till the next input is taken.
