Verilog学习笔记

本文为本人verilog学习过程中编写的代码以及对某些语法知识点的总结

 

1. 用Forever循环和disable实现5到67的计数器。

 1 `timescale 1ps/1ps
 2 module tst5_25();
 3 reg clk;
 4 reg [7:0]count;
 5 
 6 initial fork:CNT
 7   clk = 0;
 8   count = 5;
 9   forever #5 clk = ~clk;
10   forever 
11   begin
12     @(posedge clk)  //waitting for the rising edge of clk
13     count = count + 8'd1;
14     if(count ==8'd67)
15     disable CNT;
16   end
17 join
18 
19 endmodule
View Code

2. $display、$write、$strobe的不同

 $display与$write的区别在于前者自动换行

$strobe会在同一时刻的所有逻辑操作执行完后再输出。

 1 `timescale  1ps/1ps
 2 module display();
 3 
 4 reg clk,a,b;
 5 initial begin
 6   a = 1;
 7   b = 0;
 8   clk = 0;
 9   $display("dis");
10   $display("play");
11   $write("wri");
12   $write("te\n");
13   forever # 50 clk = ~clk;
14   end
15 initial begin
16   #100 $stop;
17   end
18 
19 always @(posedge clk)begin
20   b = a;
21   $strobe("b is %d",b);
22   end
23 
24 endmodule
View Code

仿真结果如下：

3. 5分频器的实现

 1 `timescale  10ps/1ps
 2 module clk_div5(clk_div5);
 3 
 4 output clk_div5;
 5 reg clk,clk1,clk2;
 6 reg [2:0]cnt1,cnt2;
 7 
 8 initial begin
 9  clk = 0;
10  clk1 = 0;
11  clk2 = 0;
12  cnt1 = 3'd0;
13  cnt2 = 3'd0;
14  forever #50 clk = ~clk;
15  end
16 
17 always @(posedge clk)begin
18   cnt1 <= (cnt1 < 4)?(cnt1 +3'd1):3'd0;
19   if(cnt1 == 2'd0)
20     clk1 <=1'b0;
21   if(cnt1 ==2'd2)
22     clk1 <=1'b1;
23   end
24   
25  always @(negedge clk)begin
26   cnt2 <= (cnt2 < 4)?(cnt2 +3'd1):3'd0;
27   if(cnt2 == 2'd0)
28     clk2 <=1'b0;
29   if(cnt2 ==2'd2)
30     clk2 <=1'b1;
31   end 
32   
33   assign clk_div5 = clk1&clk2;
34 endmodule
View Code

 

posted @ 2014-11-25 15:12  huangqiwei  阅读(271)  评论(0)  编辑  收藏  举报