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4 Data StructuresThis section describes data structures used by NVM Express.4.1 Submission Queue & Completion Queue DefinitionSections 4.1, 4.1.1 and 阅读全文
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Controller registers are located in the MLBAR/MUBAR registers (PCI BAR0 and BAR1) that shall be mapped to a memory space that supports in-order access 阅读全文
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2.6 Advanced Error Reporting Capability (Optional)The Advanced Error Reporting definitions below are based on the PCI Express 2.1 Base specification. 阅读全文
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The PCI Express Capability definitions below are based on the PCI Express 2.1 Base specification. Implementations may choose to base the device on a s 阅读全文
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Note: It is recommended that the controller allocate a unique MSI-X vector for each Completion Queue.The Table BIR and PBA BIR data structures may be 阅读全文