基于verilog状态机的交通灯演示
设计要求:设计一个简易的交通灯(系统时钟1hz共阴极)。南北方向为主干道(L3~L1),绿灯时间为29s;东西方向为次干道(L6~L4),绿灯时间为19s;在一个方向从红灯转绿灯前3s,另一个方向黄灯亮3s。
S1 S2 S3 S4 S1
主干道 红灯 红灯 绿灯 黄灯 红灯
次干道 绿灯 黄灯 红灯 红灯 绿灯
19S 3S 29S 3S 19S
module traffic(clk,rst_n,led);
input clk;
input rst_n;
output [5:0] led;
reg [5:0] led;
reg [4:0] time_left;
reg [1:0] state;
parameter [1:0] S1 = 2'b00,
S2 = 2'b01,
S3 = 2'b11,
S4 = 2'b10;
clk_div CD(
.clk(clk),
.clkout(clkout)
); //分频模块
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
state <= S1;
time_left <= 5'd18;
led <= 6'b100_001;
end
else
begin
case(state)
S1:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S2;
time_left <= 5'd2;
led <= 6'b100_010;
end
else
begin
state <= S1;
time_left <= time_left-1'b1;
led <= 6'b100_001;
end
end
end
S2:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S3;
time_left <= 5'd28;
led <= 6'b001_100;
end
else
begin
state <= S2;
time_left <= time_left-1'b1;
led <= 6'b100_010;
end
end
end
S3:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S4;
time_left <= 5'd2;
led <= 6'b010_100;
end
else
begin
state <= S3;
time_left <= time_left-1'b1;
led <= 6'b001_100;
end
end
end
S4:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S1;
time_left <= 5'd18;
led <= 6'b100_001;
end
else
begin
state <= S4;
time_left <= time_left-1'b1;
led <= 6'b010_100;
end
end
end
endcase
end
end
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/05/10 14:42:14
// Design Name:
// Module Name: clk_div
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_div(
clk, clkout
); //分频模块
input clk;
output clkout;
reg clkout;
reg [31:0] cnt;
always @(posedge clk)
begin //板子时钟为100MHZ,
if(cnt == 32'd9999_9999)
begin
clkout <= 1'b1;
cnt <= 32'b0;
end
else
begin
clkout <= 1'b0;
cnt <= cnt + 32'd1;
end
end
endmodule
而且这里采用全局时钟方式,分频后的时钟作为使能端控制数据传输。经在xilinx的xc7a100板子上验证与预想结果完全相同,设计成功。