2015年2月13日
$stop and $finish in verilog
摘要： $stop - Pauses the simulation, so you can resume it by using fg command in linux. In this case lincense will not be released and process also is not k... 阅读全文
posted @ 2015-02-13 14:59 hfyfpga 阅读(3180) 评论(1) 推荐(0) 编辑