verilog入门
写了根据闫石老师的数字电路基础写了一个一个半加器
半加器代码为
module half_adder(A,B,S,CO); input A,B; output S,CO; assign S = A^B; assign CO = A&B; endmodule
测试代码为
`timescale 1ns/1ns
module main;
reg A_tb;
reg B_tb;
wire S_tb;
wire CO_tb;
half_adder u_half_adder(
.A(A_tb),
.B(B_tb),
.S(S_tb),
.CO(CO_tb)
);
initial
begin
A_tb = 0;
B_tb = 0;
#12 A_tb = 1;
#21 B_tb = 1;
end
endmodule
全加器的代码为
module full_adder(A,B,CI,S,CO); input A,B,CI; output S,CO; assign S = ~( ((~A)&(~B)&(~CI)) | (A&(~B)&CI) | ((~A)&B&CI) | (A&B&(~CI))); assign CO = ~( (~A)&(~B) | ((~B)&(~CI)) | ((~A)&(~CI)) ); endmodule
测试代码test_bench为
`timescale 1ns/1ns
module main;
reg A_tb;
reg B_tb;
reg CI_tb;
wire S_tb;
wire CO_tb;
full_adder u_half_adder(
.A(A_tb),
.B(B_tb),
.CI(CI_tb),
.S(S_tb),
.CO(CO_tb)
);
initial
begin
CI_tb = 0 ;
A_tb = 0;
B_tb = 0;
#10
CI_tb = 0;
A_tb = 0;
B_tb = 1;
#10
CI_tb = 0;
A_tb = 1;
B_tb = 0;
end
endmodule
四位串行加法器的代码为
module serialBitAdder4(A,B,S,CO);
input [3:0] A;
input [3:0] B;
output [3:0] S;
output CO;
wire [3:0] COO;
wire [3:0] CI;
assign CI[0] = 0;
genvar i;
for(i=0;i<4;i=i+1)
begin
assign S[i] = ~( ((~A[i])&(~B[i])&(~CI[i])) | (A[i]&(~B[i])&CI[i]) | ((~A[i])&B[i]&CI[i]) | (A[i]&B[i]&(~CI[i])));
assign COO[i] = ~( (~A[i])&(~B[i]) | ((~B[i])&(~CI[i])) | ((~A[i])&(~CI[i])) );
if(i<3)
begin
assign CI[i+1] = COO[i];
end
end
assign CO = COO[3];
//module full_adder(A,B,CI,S,CO)
endmodule
当然也可以有其他更简单的写法，如调用full_adder或者直接[1]assign {CO,S}=A+B+CI;
测试代码为
`timescale 1ns/1ns
module main;
reg [3:0] A_tb;
reg [3:0]B_tb;
wire [3:0] S_tb;
wire CO_tb;
serialBitAdder4 u_serialBitAdder4(
.A(A_tb),
.B(B_tb),
.S(S_tb),
.CO(CO_tb)
);
initial
begin
A_tb = 3;
B_tb = 4;
#10
A_tb = 9;
B_tb = 6;
#10
A_tb = -1;
B_tb = 2;
end
endmodule
超前进位加法器的代码为
module carryLookHeadAdder4(CI,A,B,S,CO);
input CI;
input [3:0] A;
input [3:0] B;
output [3:0] S;
output CO;
wire [3:0] CII;
wire [3:0] COO;
wire [3:0] G;
wire [3:0] P;
genvar i;
for(i=0;i<4;i=i+1)
begin
assign G[i] = A[i]&B[i];
assign P[i] = A[i]|B[i];
end
assign CII[0] = CI;
//assign
////COO[0] = G[0]|(P[0]&CII[0]),
//COO[1] = G[1]
//COO[]
generate
genvar j;
for(j=0;j<4;j=j+1)
begin :letme
assign COO[j] = G[j] | (P[j]&CII[j]);
if(j<3)
begin
assign CII[j+1] = COO[j];
end
end
endgenerate
assign CO = COO[3];
for(i=0;i<4;i=i+1)
begin
assign S[i] = A[i]^B[i]^CII[i];
end
endmodule;
测试代码为
`timescale 1ns/1ns
module main;
reg [3:0] A_tb;
reg [3:0]B_tb;
reg CI_tb;
wire [3:0] S_tb;
wire CO_tb;
carryLookHeadAdder4 u_carryLookHeadAdder4(
.CI(CI_tb),
.A(A_tb),
.B(B_tb),
.S(S_tb),
.CO(CO_tb)
);
initial
begin
CI_tb = 0;
A_tb = 3;
B_tb = 4;
#10
A_tb = 9;
B_tb = 6;
#10
A_tb = -1;
B_tb = 2;
end
endmodule
由4个4位超前进位加法器组成的16位加法器的代码为
module cla16(CI,A,B,S,CO);
input CI;
input [15:0] A;
input [15:0] B;
output [15:0] S;
output CO;
wire [3:0] COO;
carryLookHeadAdder4 u0_carryLookHeadAdder4 (.CI(CI),
.A(A[3:0]),
.B(B[3:0]),
.S(S[3:0]),
.CO(COO[0])
);
carryLookHeadAdder4 u2_carryLookHeadAdder4 (.CI(COO[0]),
.A(A[7:4]),
.B(B[7:4]),
.S(S[7:4]),
.CO(COO[1])
);
carryLookHeadAdder4 u3_carryLookHeadAdder4 (.CI(COO[1]),
.A(A[11:8]),
.B(B[11:8]),
.S(S[11:8]),
.CO(COO[2])
);
carryLookHeadAdder4 u4_carryLookHeadAdder4 (.CI(COO[2]),
.A(A[15:12]),
.B(B[15:12]),
.S(S[15:12]),
.CO(COO[3]));
assign CO = COO[3];
endmodule
测试代码为
`timescale 1ns/1ns
module main;
reg [15:0] A_tb;
reg [15:0]B_tb;
reg CI_tb;
wire [15:0] S_tb;
wire CO_tb;
/*
carrySkipAdder u_carrySkipAdder(
.CI(CI_tb),
.A(A_tb),
.B(B_tb),
.S(S_tb),
.CO(CO_tb)
);*/
cla16 u_cla16(.CI(CI_tb),
.A(A_tb),
.B(B_tb),
.S(S_tb),
.CO(CO_tb)
);
initial
begin
CI_tb = 0;
A_tb = 3;
B_tb = 4;
#10
A_tb = 9;
B_tb = 6;
#10
A_tb = -1;
B_tb = 2;
#10
A_tb = 89;
B_tb = 26;
end
endmodule
[1] 四位全加器实现
