//实现二分频
module div2(cin,cout);
input cin;
output cout;
reg cout;
always@(posedge cin)
begin
cout<=~cout;
end
endmodule
//十进制计数器
module counter10(rst,clk,dout,cout);
input clk,rst;
output cout;
output[3:0] dout;
reg cout;
reg[3:0] dout;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
dout<=0;
cout<=0;
end
else
begin
if(dout==4'd9)
begin
dout<=0;
cout<=1;
end
else
begin
cout<=0;
dout<=dout+1;
end
end
end
endmodule
//六进制计数器
module counter6(rst,clk,dout,cout);
input clk,rst;
output cout;
output[2:0] dout;
reg cout;
reg[3:0] dout;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
dout<=0;
cout<=0;
end
else
begin
if(dout==3'd5)
begin
dout<=0;
cout<=1;
end
else
begin
cout<=0;
dout<=dout+1;
end
end
end
endmodule
//二十四进制计数器
module count24(clk,rst,dout3,dout4);
input rst,clk;
output[3:0] dout3;
output[1:0]dout4;
reg[3:0] dout3;
reg[1:0]dout4;
reg[4:0] count;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
dout3<=0;
dout4<=0;
count<=0;
end
else
begin
if(count==5'd23)
begin
count<=0;
dout3<=0;
dout4<=0;
end
else
begin
count<=count+1;
dout3<=count%5'd10;
dout4<=count/5'd10;
end
end
end
endmodule
//消抖模块
module inshake(clk,bin,bout);
input clk,bin;
output bout;
reg bin1,bin2,bin3;
always@(posedge clk)
begin
bin1<=bin;
bin2<=bin1;
bin3<=bin2;
end
wire bout=bin2|bin3;
endmodule
//或门模块
module orr(cin1,cin2,cout);
input cin1,cin2;
output cout;
assign cout=cin1+cin2;
endmodule
//六进制计数器（不带进位）
module count6(clk,cout);
input clk;
output[2:0] cout;
reg[2:0] cout;
always@(posedge clk)
begin
if(clk)
begin
if(cout==3'd5)
cout<=0;
else
cout<=cout+1;
end
else
cout<=cout;
end
endmodule
//六选一数据选择器
module select6(cin,dout1,dout2,dout3,dout4,dout5,dout6,cout);
input [2:0]cin;
input[3:0]dout1,dout3,dout5;
input[2:0]dout2,dout4;
input[1:0] dout6;
output[3:0]cout;
reg[3:0]cout;
always@(cin)
case(cin)
3'b000:cout<=dout1;
3'b001:cout<=dout2;
3'b010:cout<=dout3;
3'b011:cout<=dout4;
3'b100:cout<=dout5;
3'b101:cout<=dout6;
endcase
endmodule
//位选控制模块
module slpst(cin,cout);
input[2:0]cin;
output[5:0] cout;
reg[5:0] cout;
always@(cin)
case(cin)
3'b000:cout<=6'b111110;
3'b001:cout<=6'b111101;
3'b010:cout<=6'b111011;
3'b011:cout<=6'b110111;
3'b100:cout<=6'b101111;
3'b101:cout<=6'b011111;
default :cout<=6'b111111;
endcase
endmodule
//译码模块
module hex(cin,cout,sledpy,clkdpy);
input [3:0] cin;
output[7:0] cout;
input[2:0] sledpy;
input clkdpy;
reg dpy;
reg[7:0] cout;
always@(sledpy)
case(sledpy)
3'b100: dpy<=1;
3'b010:dpy<=clkdpy;
default : dpy<=0;
endcase
always@(cin)
case(cin)
4'd0: cout<={dpy,7'b0111111};
4'd1: cout<={dpy,7'b0000110};
4'd2: cout<={dpy,7'b1011011};
4'd3: cout<={dpy,7'b1001111};
4'd4: cout<={dpy,7'b1100110};
4'd5: cout<={dpy,7'b1101101};
4'd6: cout<={dpy,7'b1111101};
4'd7: cout<={dpy,7'b0000111};
4'd8: cout<={dpy,7'b1111111};
4'd9: cout<={dpy,7'b1101111};
endcase
endmodule
//顶层文件模块
module digitalclock(HAdd,MAdd,f2,f512,f64,rst,hexpin,hexsle);
input HAdd,MAdd,f2,f512,f64,rst;
output[5:0] hexsle;
output[7:0] hexpin;
wire line1,line2,line3,line4,line5,line6,line7,line8,line9,line10,line11;
wire[2:0] w2,w4,out;
wire[3:0] w1,w3,w5,w7;
wire[1:0] w6;
div2 u1(.cin(f2),.cout(line1));
counter6 u2(.rst(rst),.clk(line2),.dout(w2),.cout(line3));
counter10 u3(.rst(rst),.clk(line1),.dout(w1),.cout(line2));
counter6 x2(.rst(rst),.clk(line9),.dout(w4),.cout(line6));
counter10 x3(.rst(rst),.clk(line5),.dout(w3),.cout(line9));
count24 u4 (.clk(line8),.rst(rst),.dout3(w5),.dout4(w6));
inshake u5 (.clk(f64),.bin(MAdd),.bout(line4));
inshake u6 (.clk(f64),.bin(HAdd),.bout(line7));
orr u8(.cin1(line3),.cin2(line4),.cout(line5));
orr u9(.cin1(line6),.cin2(line7),.cout(line8));
count6 u10(.clk(f512),.cout(out));
slpst u11(.cin(out),.cout(hexsle));
select6 u12(.cin(out),.dout1(w1),.dout2(w2),.dout3(w3),.dout4(w4),.dout5(w5),.dout6(w6),.cout(w7));
hex u13(.cin(w7),.cout(hexpin),.sledpy(out),.clkdpy(line1));
endmodule
