【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch12
摘要:
Chapter 12. User-Defined Primitives 12.7 Exercises 1. Design a 2-to-1 multiplexer by using UDP. The select signal is s, inputs are i0,i1, and the output is out. If the select signal s=x, the output ou... 阅读全文
posted @ 2011-03-28 16:53 yf.x 阅读(2318) 评论(0) 推荐(0) 编辑