【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch10
摘要：
Chapter 10. Timing and Delays10.6 Exercises1. What type of delay model is used in the following circuit? Write the Verilog description for the module Y. my answer: Distributed Delay. 2. Use the largest delay in the module to convert the circuit to a lumped delay model. Using a lumped delay model, wr 阅读全文
posted @ 2011-03-25 20:13 yf.x 阅读(3268) 评论(0) 推荐(0) 编辑
