【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch09
摘要：
Chapter 9. Useful Modeling Techniques9.7 Exercises1. Using assign and deassign statements, design a positive edge-triggered D-flipflop with asynchronous clear(q=0) and preset (q=1). my answer: 2. Using primitive gates, design a 1-bit full adder FA. Instantiate the full adder inside a stimulus module 阅读全文
posted @ 2011-03-24 17:33 yf.x 阅读(6247) 评论(0) 推荐(0) 编辑
