摘要： 7. Design a negative edge-triggered D-flipflop(D_FF) with synchronous clear, active high (D_FF clears only at a negative edge of clock when clear is high). Use behavioral statements only. (Hint: Output q of D_FF must be declared as reg). Design a clock with a period of 10 units and test the D_FF.my 阅读全文

摘要： Chapter 7. Behavioral Modeling7.11 Exercises1. Declare a register called oscillate. Initialize it to 0 and make it toggle every 30 time units. Do not use always statement ( Hint: Use the forever loop).my answer:2. Design a clock with time period = 40 and a duty cycle of 25% by using the always and i 阅读全文